Ahmed Benhassain

Adaptive Wearout Management with in-situ aging monitors

In this work, the fundamental elements towards an Adaptive Wearout Management (AWM) of digital circuits are presented including a new generation of in-situ aging monitors. The warning flags allow circuits to execute instructions in a fault-free way with large power savings up to 40%.

Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI

Aging induced degradation mechanisms occurring in digital circuits are of a greater importance in the latest technologies. Monotonic degradation such as Bias Temperature Instability (BTI) or Hot Carrier Injection (HCI) but also sudden degradation such as Dielectric Breakdown (DB) are identified as the major sources of reliability hazard. The impact of these phenomena on the digital circuits is usually observed in terms of timing degradations and thus may result in setup/hold violation. In this paper we will focus on the impact of aging related degradation mechanisms on timing. In-situ monitor is a promising strategy to measure timing slacks and to provide pre-error warnings prior to timing violation. In this paper, we have developed a dedicated test structure to measure and benchmark the behavior of different monitors. The design of monitors is mostly based on delay elements. Three types of delays are proposed in this paper: flip-flops Master delay, Buffers delay and Passive delay. In addition, we investigate the impact of global and local variations on the accuracy of the measurements by providing complete monitors characterization. The technology used for the test structure and in-situ monitors is 28nm Fully Depleted Silicon On Insulator. Experimental results show a good agreement with SPICE simulation. Finally the proposed in-situ monitors will be compared and their applications to circuit aging prediction will be discussed.

Timing in-situ monitors: Implementation strategy and applications results

In-situ monitor is a promising strategy to measure timing slacks and to provide pre-error warning prior to any timing violation. In this work, we demonstrate that the usage of in-situ monitors with a feedback loop of voltage regulation is suitable for process compensation, multiples OPP modes, temperature and ageing compensation.

Dynamic adaptive voltage scaling in automotive environment

A novel control loop enables Dynamic Adaptive Voltage Scaling in a demonstrator with digital cores tightly coupled with monitors and Dynamic Controller. Control loop robustness is validated by Markov chains and experimental results. Monitors allow circuits to execute instructions from workloads in fault-free way with power savings up to 50%.

Robustness of timing in-situ monitors for AVS management

Aggressive speed roadmap for consumer product requires performance boost with power management policies under wear-out, process, voltage and temperature variations. In-Situ timing Monitors is a promising solution for adaptive wear-out management solutions and more generally it helps minimize all voltage margins related to manufacturing variations and operating conditions. A complete insertion of monitor scheme in industrial digital flow is presented. The impact of arbitrarily selection of path under monitoring is widely discussed. The coverage (amount of path monitored in reference PVT vs worst critical path monitored in arbitrary PVT) is at first order dependent on voltage. Measurement of time detection windows of inserted monitors is presented for 28FDSOI and 40nm bulk technologies from ST-Microelectronics. In addition, a counter of ISM warnings is implemented and measurements are shown for different workloads, temperatures, frequency operations and ISM time windows on large samplings.

In-situ slack monitors: taking up the challenge of on-die monitoring of variability and reliability

For advanced CMOS technology nodes, the global/local variability is challenging to handle during conception. In-situ monitor (ISM) is suitable to minimize all margins related to manufacturing variations and operating conditions. After the introducing the ISM concept, a complete insertion scheme is presented in industrial flow. A dedicated test chip is developed where ISMs are inserted in a digital block. An intensive measurement campaign is performed, and results are deeply investigated. Various effects like temperature, voltage, and ISM time window are analyzed both at IP level (Fmax/Vmin) and at gate cell level (critical path) on large sampling and compared to different hierarchal tools (spice, timing analysis, activity by power estimation tool).

Architecture- and workload-dependent digital failure rate

The ability to determine product failure rate at the design conception stage would serve as a feedback to the design teams to create robust designs. IP hardening leading to a long lasting reliable product portfolio is the need of the hour for the upcoming IOT and Smart Driving Markets. Conventional aged static timing analysis does not take into account the aging due to the digital circuit workload at operational lifetime and a degradation modulation of 2–3X is observed. But, workload dependent digital circuit reliability analysis has been made possible with models that predict the aged standard cell behavior for its corresponding operational stress. This paper thus leverages the workload dependent reliability analysis for early product failure rate calculations.

Investigation of critical path selection for in-situ monitors insertion

The performance and low power requirement are becoming more and more challenging to fulfill for consumer product. On the opposite, a low failure rate at SoC level must be guaranteed to the end-customer. In that context, the insertion of in-situ slack monitor is known to be promising and efficient solution to manage the wear-out and more generally to minimize all margins related to manufacturing variations and operating conditions. As far as in-situ slack monitors are located in functional path, the choice of endpoint register and the number of monitors are of prime importance. This paper deals with a methodology of path selection in a context of monitor insertion in digital block without pattern availability. Basically, the timing of data path arriving to an endpoint register is analyzed, and a weight is calculated as a figure of merit. This work accounts for stochastic dispersion, aging, global corner process, voltage and temperature variations. The important role played by the sub-critical path is illustrated with silicon measurement.

Dynamic aging compensation and Safety measures in Automotive environment

New insights on the stochastic nature of aging-related timing impact in digital circuits trigger the need for aging compensation control loop. Such control loops enable additional 22% power savings but require dedicated safety measures (either margin or monitoring) to enable fault-free operations even in cases of out-of-specifications usage.

Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results

With CMOS technology scaling, it becomes more and more difficult to guarantee circuit functionality for all process, voltage, temperature (PVT) corners. Moreover, circuit wear-out degradation lead to additional temporal variations, resulting in an important increase of design margins when targeting specific reliable systems (automotive or health care embedded applications) [1]. Adding pessimistic timing margin to guarantee all operating points under worse case conditions is no more acceptable due to the huge impact on design costs, such as up to 10% increase of slack time, with an upward trend as technology moves further.