S. Mhira

Mission profile recorder: An aging monitor for hard events

This work demonstrates the fundamental aspects of Mission Profile Recording as an alternative to intrusive, aging monitoring systems to cope with oxide breakdown and electromigration degradation mechanisms. A functional prototype is designed, implemented and fully tested on several wafers to achieve a full proof-of-concept. This study offers new perspectives towards product hardening and qualification with respect to an adaptive approach to real user-based workloads.

Robust automotive products in advanced CMOS nodes

In this work, additional elements needed on top of conventional foundry reliability knowledge to enable robust automotive products in compliance with all restrictive norms are introduced. For intrinsic reliability, the main element is the reliability models (a design compatible WLR description). Their usage for design margins definition and their thorough validation at IP level is described. For extrinsics failure, two different screening procedures, Vstress and Burn-In (conventional or wafer-level), are here well documented and in use for volume production to bring the failure rate level down below 1ppm automotive target. Altogether, the global approach developed in STMicroelectronics enable robust automotive products based on controlled and validated procedures.

Dynamic adaptive voltage scaling in automotive environment

A novel control loop enables Dynamic Adaptive Voltage Scaling in a demonstrator with digital cores tightly coupled with monitors and Dynamic Controller. Control loop robustness is validated by Markov chains and experimental results. Monitors allow circuits to execute instructions from workloads in fault-free way with power savings up to 50%.

Robustness of timing in-situ monitors for AVS management

Aggressive speed roadmap for consumer product requires performance boost with power management policies under wear-out, process, voltage and temperature variations. In-Situ timing Monitors is a promising solution for adaptive wear-out management solutions and more generally it helps minimize all voltage margins related to manufacturing variations and operating conditions. A complete insertion of monitor scheme in industrial digital flow is presented. The impact of arbitrarily selection of path under monitoring is widely discussed. The coverage (amount of path monitored in reference PVT vs worst critical path monitored in arbitrary PVT) is at first order dependent on voltage. Measurement of time detection windows of inserted monitors is presented for 28FDSOI and 40nm bulk technologies from ST-Microelectronics. In addition, a counter of ISM warnings is implemented and measurements are shown for different workloads, temperatures, frequency operations and ISM time windows on large samplings.

Potentiality of healing techniques in hot-carrier damaged 28 nm FDSOI CMOS nodes

We have developed the possibility of using healing phases on hot-carrier (HC) degraded transistors from devices to logic cells (1) by the combined effects of oxide charge neutralization and channel shortening (2) using back bias V-B sensing effects in forward (FBB) mode in 28 nm FDSOI CMOS node. This is done for DC to AC operations from Input-Output device (EOT = 3.6 nm) to core blocks (EOT = 135 nm) leading to an almost complete cure of HC damaged devices for digital application. Continuous or short sequences of healing phases help to regenerate HC degraded parameters (I-on, V-T) offering new perspectives for on time repeatedly cure digital operation as well as under some analog case

In-situ slack monitors: taking up the challenge of on-die monitoring of variability and reliability

For advanced CMOS technology nodes, the global/local variability is challenging to handle during conception. In-situ monitor (ISM) is suitable to minimize all margins related to manufacturing variations and operating conditions. After the introducing the ISM concept, a complete insertion scheme is presented in industrial flow. A dedicated test chip is developed where ISMs are inserted in a digital block. An intensive measurement campaign is performed, and results are deeply investigated. Various effects like temperature, voltage, and ISM time window are analyzed both at IP level (Fmax/Vmin) and at gate cell level (critical path) on large sampling and compared to different hierarchal tools (spice, timing analysis, activity by power estimation tool).

Architecture- and workload-dependent digital failure rate

The ability to determine product failure rate at the design conception stage would serve as a feedback to the design teams to create robust designs. IP hardening leading to a long lasting reliable product portfolio is the need of the hour for the upcoming IOT and Smart Driving Markets. Conventional aged static timing analysis does not take into account the aging due to the digital circuit workload at operational lifetime and a degradation modulation of 2–3X is observed. But, workload dependent digital circuit reliability analysis has been made possible with models that predict the aged standard cell behavior for its corresponding operational stress. This paper thus leverages the workload dependent reliability analysis for early product failure rate calculations.

Investigation of critical path selection for in-situ monitors insertion

The performance and low power requirement are becoming more and more challenging to fulfill for consumer product. On the opposite, a low failure rate at SoC level must be guaranteed to the end-customer. In that context, the insertion of in-situ slack monitor is known to be promising and efficient solution to manage the wear-out and more generally to minimize all margins related to manufacturing variations and operating conditions. As far as in-situ slack monitors are located in functional path, the choice of endpoint register and the number of monitors are of prime importance. This paper deals with a methodology of path selection in a context of monitor insertion in digital block without pattern availability. Basically, the timing of data path arriving to an endpoint register is analyzed, and a weight is calculated as a figure of merit. This work accounts for stochastic dispersion, aging, global corner process, voltage and temperature variations. The important role played by the sub-critical path is illustrated with silicon measurement.

Dynamic aging compensation and Safety measures in Automotive environment

New insights on the stochastic nature of aging-related timing impact in digital circuits trigger the need for aging compensation control loop. Such control loops enable additional 22% power savings but require dedicated safety measures (either margin or monitoring) to enable fault-free operations even in cases of out-of-specifications usage.

Workload dependent reliability timing analysis flow

Silicon measurements indicate a change in frequency limiting path rankings as per aging and also as a function of workload. This paper proposes a simulation flow that leads to the identification of workload specific aged critical paths. Gate-level models are a means to estimate aging of the critical paths by taking into consideration the stress experienced by corresponding standard cells for a given digital circuit workload during circuit operational lifetime. We thus estimate the workload based aging margins for a particular design using this simulation flow.