F. Cacho

BTI variability fundamental understandings and impact on digital logic by the use of extensive dataset

This paper presents understandings on BTI variability based upon an extensive dataset. This enables to select between various theoretical statistical models and to propose a novel description approach for the NBTI-induced mismatch for different technological nodes and a comparison with time-zero variability. The impact from transistor to gate level is also evaluated.

Managing SRAM reliability from bitcell to library level

Static Random Access Memories (SRAMs) are present nowadays in all CMOS products in large quantities. Besides, they are often very challenging both on process side (due to small dimensions) and on design side (due to performance request). As a consequence, managing their reliability is of prime importance, though it is quite complex due to their overall complexity. This paper demonstrates a full reliability-based design flow for SRAM libraries including both Front-End degradation modes (NBTI, PBTI and HCI) as well as Back-End degradation modes (Electromigration). Large experimental datasets on various technologies and SRAM bitcells have been used all along the paper to show clear Silicon-CAD correlation evidences, demonstrating the efficiency and accuracy of the developed flow.

A predictive bottom-up hierarchical approach to digital system reliability

This work has introduced a new electrical aging assessment framework for digital systems, based upon strong physics-based foundations and an adequate bottom-up approach which enables propagating accurate reliability knowledge at system level. This work opens new ways to optimize high level digital systems with respect to aging with great accuracy.

A bottom-up approach for System-On-Chip reliability

Abstract We demonstrate here for the first time that it is possible by a bottom-up approach to build transistor- and gate-level models with enough accuracy to allow direct comparison with experimental degradations at system-level. This work opens new ways to optimize high level digital systems with respect to aging with great accuracy.

HCI/BTI coupled model: The path for accurate and predictive reliability simulations

The standard qualification of CMOS Wafer Level Reliability by manufacturers consists in qualifying BTI mechanism from one side and HCI from another side independently. Their respective degradation are then assumed to be additive. Here, we study the interaction between both mechanisms through alternative stress sequences at device level and also in ring oscillators. Interaction formalism is proposed and implemented in Design-in-Reliability simulation framework. While two ageing mechanisms co-exist and are interacting, we consider the origin of mechanisms (non-conducting HCI, low-E HCI...) and quantify the weight of coupling. We also point out that without this interaction consideration in Design-in-Reliability simulation, results are significantly inaccurate and pessimistic. Finally, we present degradation results for a large amount of standard cell RO-based at package level, at different stress/time conditions and conclude that this feature of simulation is a must have in logic Design Platform characterization in order to avoid over-estimation of timing degradation.

Impact of the gate-stack change from 40nm node SiON to 28nm High-K Metal Gate on the Hot-Carrier and Bias Temperature damage

High-K Metal-Gate 28nm node (C28) with equivalent gate-oxide thickness EOT= 1.35nm has been compared to low power 40nm CMOS node (1.7nm) on silicon bulk. Hot-Carrier damage in C28 originates from the same permanent ΔNIT mechanism under current driven Multiple Particle (MP) interactions, relative to the SiON interface layer while border to bulk oxide traps make the larger difference between NMOS and PMOS transistors. This has been obtained by their respective temperature activation and AC response behaviors at Room Temperature and High Temperature due to the distinct proportion of accessible shallow/deep defects in the HK-MG structures.

Reliability Characterization and Modeling Solution to Predict Aging of 40-nm MOSFET DC and RF Performances Induced by RF Stresses

In the framework of MOSFET reliability for RF/AMS applications, a deep investigation of RF parameters degradation is performed. An innovative flow, composed of DC and RF stresses with DC and RF aging characterization, is presented. Degradation kinetics of main parameters are physically explained and modeled using PSP compact model to predict the behavior of stressed devices.

28nm node bulk vs FDSOI reliability comparison

In this paper, we present TDDB, HCI and BTI reliability characterization of Nfet and Pfet devices issued from FDSOI and bulk 28nm technologies. 28nm FDSOI devices achieve 32% improved performance, 40% reduced power consumption and improved matching. From device level tests, 28nm FDSOI also demonstrates intrinsic reliability behavior similar to 28 bulk devices, giving confidence in the robustness of this technology.

Technology scaling and reliability: Challenges and opportunities

This paper reviews the challenges in reliability degradation and modeling triggered by the unwavering technology scaling. By an adequate modeling and choice of tools, the challenges can be turn out to opportunities to enhance IPs and products performances through an accurate trade-off with reliability.

Bias temperature instability and hot carrier circuit ageing simulations specificities in UTBB FDSOI 28nm node

We present new reliability features related to the use of a wide range of bulk back biasing in advanced UTBB FDSOI devices. NBTI and HCI stresses were done addressing degradation dependencies vs. bulk bias with the help of TCAD simulations in order to validate our new proposed NBTI physical model in UTBB FDSOI CMOS node.