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Dive into the research topics where V. Huard is active.

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Featured researches published by V. Huard.


international reliability physics symposium | 2004

Hole trapping effect on methodology for DC and AC negative bias temperature instability measurements in PMOS transistors

V. Huard; M. Denais

This works presents a thorough study of adequate methodology to be used in order to characterize the NBTI degradation by taking into account the transient effects. The hole trapping/detrapping effect on previously existent traps is the dominant origin of the transient effect and not the interface traps passivation by hydrogen atoms diffusing back to the interface.


international reliability physics symposium | 2003

Evidence for hydrogen-related defects during NBTl stress in p-MOSFETs

V. Huard; F. Monsieur; G. Ribes; S. Bruyere

This work gives an insight into the degradation mechanisms during a negative bias instability stress on ultrathin oxides (t/sub ox/=20 /spl Aring/). The generation of interface traps and oxide defects is shown to impact parameters such as the threshold voltage. Their generation is linked to the release of hydrogen species at the interface according to the hydrogen release model. Only hot holes can be trapped by the anode hole injection phenomenon.


international reliability physics symposium | 2006

New Insights into Recovery Characteristics Post NBTI Stress

Cr Parthasarathy; M Denais; V. Huard; G. Ribes; E. Vincent; A. Bravaix

In this work, we investigate recovery characteristics post NBTI stress when the recovery bias remains negative but lower in magnitude than the stress bias, consolidating the viewpoint involving role of hole trapping during NBTI degradation. We show that successive negative recovery biases can be applied to view trapping and detrapping behavior explicitly


international reliability physics symposium | 2006

Paradigm Shift for NBTI Characterization in Ultra-Scaled CMOS Technologies

M. Denais; A. Bravaix; V. Huard; C. Parthasarathy; C. Guerin; G. Ribes; Franck Perrier; M. Mairy; D. Roy

We have proposed a new methodology to study both DC and AC NBTI effects taking into account both the recoverable property of the degradation and the electrical parameter legitimacy in each electrical configuration. In this new framework, characterization phases induce no effect (neither recovery nor extra-damage) on the degradation. For DC NBTI with a partial/uniform recovery, a generalized universal recovery modelling has been proposed for the first time to estimate the recovery amount. This modelling is particularly useful to calculate the recovery time needed after a stress period to reach a (decrease) degradation amount. For AC NBTI case, NBTI has been directly studied on circuits parameters opening new promising perspectives in term of reliability criteria


international reliability physics symposium | 2006

Physical Modeling of Negative Bias Temperature Instabilities for Predictive Extrapolation

V. Huard; C.R. Parthasarath; C. Guerin; M. Denais

Based on new insights on measurement methodologies, interface traps creation and hole trapping as root causes of NBTI degradation are investigated in this paper. Physical modeling is proposed and the related extrapolation laws are discussed


international integrated reliability workshop | 2005

Single-hole detrapping events in pMOSFETs NBTI degradation

V. Huard; C. Parthasarathy; M. Denais

This work shows that the recovery of NBTI degradation in ultra-small gate area pMOSFETs presents abrupt steps which are related to the detrapping of one hole. These results can be obtained by using a new approach to monitor the recovery, which is extremely more sensitive than previously proposed methodology. This result opens the way to model the NBTI degradation for ultra-small gate area devices which are main components of SRAM cells.


international reliability physics symposium | 2007

The Energy-Driven Hot Carrier Degradation Modes

C. Guerin; V. Huard; A. Bravaix

In this work, we confirm that the energy is the driving force of hot carrier effects. In the high energy-, long channel-case, the LEM picture is still valid. But when the energy is lowered, high energy electrons generated by electron-electron scattering (EES) become the dominant contribution to the degradation. Finally, for even lower energy, the hot carrier degradation becomes a composite mode combining both multiple vibrational excitation (MVE) mechanism (Hess, 1999) and medium-energy electrons heated by EES (Rauch, 2001)


international reliability physics symposium | 2007

Unified Perspective of NBTI and Hot-Carrier Degradation in CMOS using on-the-Fly Bias Patterns

C. Parthasarathy; M. Denais; V. Huard; C. Guerin; G. Ribes; E. Vincent; A. Bravaix

This work views NBTI and various conditions of channel hot carrier (CHC) degradation in PMOS and NMOS devices from a unified perspective. This is accomplished by a novel technique using sequential application of stress biases and monitoring the degradation on-the-fly. Thereby, we are able to observe and segregate the distinct mechanisms co-existing during a particular condition of degradation. In particular, we gain critical insights into recovery phenomena, which are observed during certain conditions of CHC degradation (Mistry et al., 1991) as well as during NBTI (Rangan, 2003). These findings set the stage for consistent physical models for degradation as well as for design simulation under multiple operating modes


international integrated reliability workshop | 2006

Impact of Hot Carrier Degradation Modes on I/O nMOSFETS Aging Prediction

C. Guerin; V. Huard; A. Bravaix; M. Denais

This work shows that channel hot carrier (CHC) in nMOSFET consists in two different regimes depending on the gate voltage (Vg). At low Vg, a simple way to extrapolate lifetime at nominal bias conditions from data get under accelerated stress conditions will be detailed. At high Vg, the second degradation mode becomes worse depending on Vd. This work focuses on the worst case degradation determination and the model effects on the device lifetime prediction in relation to the CHC degradation mechanisms. A combined and complementary use of charge pumping (CP) and direct current current voltage (DCIV) allows us to obtain the spatial interface traps (Nit) localization giving more information on Nit impact on linear transistor parameters degradation


international symposium on the physical and failure analysis of integrated circuits | 2007

New Hot-Carrier Lifetime Technique for High- to Low-Supplied Voltage nMOSFETs

C. Guerin; C. Parthasarathy; V. Huard; A. Bravaix

In this paper, we propose to distinguish the distinct carrier degradation modes as a function of the energy range developing a complete lifetime extrapolation technique down to the low voltage operation. This provides a starting point of a more accurate modeling of CHC effects during product operations. This work shows that CHC effects in nMOSFET consist in three different regimes depending on the gate voltage (Vg). A simple way to extrapolate lifetime at nominal bias conditions from data get under accelerated stress conditions was detailed for each regime. We also propose an answer to the contradictory debate of the respective contributions of electron-electron scattering (EES) (Rauch et al., 2001) and the multiple vibrational excitation (MVE) (Hess et al., 1999) to CHC effects in the low energy range.

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A. Bravaix

Centre national de la recherche scientifique

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