Ahmed Eladawy

A novel fully differential current conveyor and applications for analog VLSI

In this paper, a novel fully differential second-generation current conveyor (FDCCII) is presented. The proposed block is useful in mixed-mode applications where fully differential signal processing is required. Furthermore, the FDCCII can be used to realize MOSFET-C filters. The circuit has a bandwidth of about 10 MHz under heavy capacitive loads and can operate from low supply voltages down to /spl plusmn/1.5 V.

Boost Converter With Dynamic Input Impedance Matching for Energy Harvesting With Multi-Array Thermoelectric Generators

This paper presents a built-in input matching technique capable of handling a wide variation of multi-array thermoelectric generator (TEG) impedances ranging two decades, from 10 s to 1000 s of ohms. Maximum power point tracking (MPPT) control for a boost converter (BC) is introduced. The analytical expressions derived offer insight on the manner in which MPPT interacts with a BC to achieve best performance. The BC operates in a discontinuous conduction mode under pulse frequency modulation to minimize power consumption and maximize efficiency for light loads. Losses are minimized by implementing a pseudo-zero current switching control via the PMOS switch on/off time, and the output voltage is set using a global clocked comparator. A prototype was fabricated in 0.5 μm CMOS where efficiency measurements showed a maximum value of 61.15% for an RTEG = 33.33 Ω, and quiescent power consumption was 1 μW.

Low voltage fully differential CMOS voltage mode digitally controlled variable gain amplifier

In this paper, a voltage mode variable gain amplifier (VGA) is presented. A fully differential implementation is used to suppress the common mode noise and increase the dynamic range. The gain of the proposed VGA can be digitally controlled from 0 to 53 dB, with a 1 dB resolution. The gain control is performed in two stages; coarse control with a 6 dB resolution and fine control with a 1 dB resolution. Simulation shows that the bandwidth is about 15 MHz at the maximum gain (53 dB). The differential output third intercept point (OIP3) is 4 V.

A low-voltage single input class AB transconductor with rail-to-rail input range

A new CMOS programmable rail-to rail transconductor is presented. A linear V-I characteristic is obtained by using the principle of nonlinearity cancellation of matched MOS transistors operating in the ohmic region. Rail-to-rail operation is achieved by using two complementary blocks. The circuit is suitable for low voltage as it can operate from supply voltages down to /spl plusmn/1.5 V. PSpice simulations show that the transconductance gain can be electronically tuned from 13 to 90 /spl mu/ A/V with bandwidth of about 40 MHz.

A Novel 10-Bit 2.8-mW TDC Design Using SAR With Continuous Disassembly Algorithm

This brief introduces a successive approximation time-to-digital converter based on a novel algorithm denoted as successive approximation register with continuous disassembly (SAR-CD). The main advantage of the proposed SAR-CD algorithm is that it moves the conditioning between the evaluated bits to the digital domain, after all the bits are evaluated. Simulation results show promising enhancements in power consumption compared with the state-of-the-art designs. A full 10-bit architecture is introduced using 65-nm CMOS technology as a case study with simulation power consumption of 2.8 mW at a sampling rate of 29.4 Msample/s from 1-V power supply with an effective number of bits value of 8.63 bits and a maximum differential nonlinearity of 1 least significant bit.

Fully integrated high accuracy continuous current sensor for switching voltage circuits

This paper presents the design of a novel integrated continuous current sensor (CCS) circuit for class-D audio amplifier and current mode controlled DC-DC converter. The proposed current sensor has the capability of sensing either positive or negative current of off-chip inductor continuously. Additionally, fast transient response with low quiescent current has been achieved. Furthermore, a calibration technique has been developed and attached to current sensor circuit to eliminate performance deterioration due to process, supply, and temperature (PVT) variation. The proposed CCS has been implemented using TSMC 65 nm technology. Simulation results show that the proposed CCS is able to operate with switching frequency up to 1 MHz at only 75 μA quiescent current. The overall accuracy of proposed CCS is greater than 95% over all process corners and temperature variation from -40°C to 125°C, and supply variation from 2.5 V to 2.9 V.

A low-power area-efficient design and comparative analysis for high-resolution neural data compression

Nowadays, brain scientific research progress depends on signal compression at high spatial resolutions, for efficient storage and low-rate transmission through wireless connection to outside world. So that neural data compression at the implant site is necessary in order to conform with the wireless rates restrictions. In this paper, the high spatial correlation is utilized to increase the data compression ratio. Then we investigate and compare three different proposed low-power image compression algorithms based on discrete cosine transform (DCT) and discrete wavelet transform (DWT) to provide the best trade-off between hardware complexity and compression performance. Hence, we conclude that Adaptive 2D-DWT algorithm is a promising solution for low-power implantable devices.

TDC SAR algorithm with continuous disassembly (SAR-CD) for time-based ADCs

This paper introduces a new algorithm and circuit design of Time-to-Digital Converter(TDC) with modified Successive Approximation Register(SAR) algorithm. This design enables continuous pulse disassemble. The input pulse is absolutely compared to pulses of widths proportional to Vfs/2, Vfs/4..Vfs/N, and each bit is evaluated independent of the previous bit result. Then bits correction is applied after the sample evaluation. A 4bit case study circuit is realized using TSMC CMOS 65nm design technology. The design demonstrated 3.67 Effective Number Of Bits (ENOB) for a sampling frequency of 666 MS\s.

Low Voltage Low Power Fully Differential CMOS Current Mode Digitally Controlled Variable Gain Amplifier

By Ahmed A. EI-Adawy* and Ahmed M. Soliman* Abstract In this paper, a fully differential current mode variable gain amplifier (VGA) is presented. The gain of the proposed VGA can be digitally controlled from 0 dB to 50.7 dB, with a 2.8 dB step. The proposed VGA consists of two coarse control stages with a gain step of 16.9 dB and a fine control stage with a gain step of 3.38 dB. A novel current division technique is used to control the gain of the VGA. SpectreS simulations based on the AMI 0.5 pm -well BSIM3 parameters are in agreement with the presented work. Simulations showed that the bandwidth is about 50MHz at the maximum gain (50.7 dB). Owing to the class AB operation of the proposed VGA circuit, the power dissipation is about 1.5 mW and the equivalent input referred noise is 2.76 pA/VRz\

Mm Wave LNA Using feedback guanella transmission line transformer

This work aims to present the post layout simulation of a fully differential implementation of two-stage low noise amplifier (LNA) using feedback transformer in TSMC 65nm CMOS technology. The transformer is used to neutralize with Miller capacitance of the FET. Guanella transmission line transformer (TLT) is implemented using coupled transmission line. This transformer is easier to design than other conventional types of transformers. The LNA achieves transducer gain (Gt) of 12.2dB with noise figure (NF) of 4.27dB and IIP3 is 5.6dBm, while it consumes 30mW from 1.2v. This design has almost a perfect input output isolation of more than 60dB.