Faisal A. Hussien

An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing

Current and future integrated systems demand cost-effective test solutions. In response to that need, this work presents a very compact mixed-signal test system. It performs the characterization of the magnitude and phase responses over frequency at multiple nodes of an analog circuit. The control inputs and output of this system are digital, enabling the test of the analog components in a system-on-chip (SoC) or system-in-package (SiP) through a low-cost digital automatic test equipment. Robust and area-efficient building blocks are proposed for the implementation of the test system, including a linearized analog multiplier for accurate magnitude and phase detection, a wide tuning range voltage-controlled oscillator and a low-power algorithmic analog-to-digital converter. Their individual design considerations and performance results are presented. A complete prototype in TSMC CMOS 0.35-mum technology employs only 0.3mm2 of area. The operation of this test system is demonstrated by performing frequency response characterizations up to 130 MHz at various nodes of two different fourth-order continuous-time filters integrated in the same chip

Design considerations and tradeoffs for passive RFID tags

Radio Frequency Identification (RFID) systems are widely used in a variety of tracking, security and tagging applications. Their operation in non line-of-sight environments makes them superior over similar devices such as barcode and infrared tags. RFID systems span a wide range of applications: medical history storage, dental prosthesis tracking, oil drilling pipe and concrete stress monitoring, toll ways services, animal tracking applications, etc. Passive RFID tags generate their power from the incoming signal; therefore, they do not require a power source. Accordingly, minimizing the power consumption and the implementation area are usually the main design considerations. This paper presents a complete analysis on designing a passive RFID tag. A system design methodology is introduced including the main issues and tradeoffs between different design parameters. The uplink modulation techniques used (ASK, PSK, FSK, and PWM) are illustrated showing how to choose the appropriate signaling scheme for a specific data rate, a certain distance of operation and a limited power consumption budget. An antenna system (transmitter and receiver) is proposed providing the maximum distance of operation with the transmitted power stated by FCC regulations. The backscatter modulation scheme used in the downlink is shown whether to be ASK-BM or PSK-BM and the differences between them are discussed. The key building blocks such as the charge pump, voltage reference, and the regulator used to generate the DC supply voltage from the incoming RF signal are discussed along with their design tradeoffs. A complete architecture for a passive RFID tag is provided as an example to illustrate the proposed RFID tag design methodology.

Fully integrated high accuracy continuous current sensor for switching voltage circuits

This paper presents the design of a novel integrated continuous current sensor (CCS) circuit for class-D audio amplifier and current mode controlled DC-DC converter. The proposed current sensor has the capability of sensing either positive or negative current of off-chip inductor continuously. Additionally, fast transient response with low quiescent current has been achieved. Furthermore, a calibration technique has been developed and attached to current sensor circuit to eliminate performance deterioration due to process, supply, and temperature (PVT) variation. The proposed CCS has been implemented using TSMC 65 nm technology. Simulation results show that the proposed CCS is able to operate with switching frequency up to 1 MHz at only 75 μA quiescent current. The overall accuracy of proposed CCS is greater than 95% over all process corners and temperature variation from -40°C to 125°C, and supply variation from 2.5 V to 2.9 V.

An adaptive slew rate and dead zone ring amplifier

This paper presents an adaptive ring amplifier that introduces a degree of freedom in speed/stabilization design trade-off in the original ring amplifier. It also introduces an area efficient solution for the auto-zeroing stability problem that the conventional ring amplifier suffers from. The proposed adaptive ring amplifier improves the linearity by 10dB at the same opera ting frequency. Moreover, it achieves a 40% improvement in the operating frequency for the same linearity and settling requirements. The proposed ring amplifier has been implemented and simulated in a low-cost CMOS 130nm technology while operating from a single 1.2V supply. It has a 98% area reduction compared to the conventional ring amplifier for the same stability conditions.1

A 3dB NF 0.1–6.6GHz inductorless wideband low-noise amplifier in 0.13µm CMOS

An inductorless wideband LNA is designed with low NF and high linearity. It is based on the use of both passive and active feedback with current reuse techniques to achieve the required low NF, high BW, and suitable gain. An auxiliary transistor is added to the differential implementation to achieve a high linearity. The circuit is designed in 0.13μm TSMC technology and exhibits a gain of 18.4dB over an entire bandwidth of 6.6GHz. Across the whole band of interest, the NF does not exceed 3dB, while the IIP3 is maintained above 6dBm, and it consumes 13.4mW DC power from a 1.5V supply.

Design consideration for LPF with gain boosting in GHz-range applications

A 0.18 mum CMOS fifth order Butterworth low-pass filter with 24 dB programmable gain boost at its 1.2 GHz cut-off frequency for HDD applications is presented. A new Gm-LC architecture is proposed using feedforward path techniques to achieve the required boost. The gain of the feedforward path can be controlled to provide the variable boost. Simulation results shows that a 28/46 mA is drawn from a 1.8 V supply in the no-boost/max-boost cases respectively. Group delay variations for different boost values are limited to 10% from the no-boost case. At the nominal output voltage swing of 250 mVpp at 1.2 GHz, a THD of -42 dB is obtained

A Low-Distortion High-Efficiency Class-D Audio Amplifier Based on Sliding Mode Control

This brief presents a low-power low-distortion high-efficiency class-D audio amplifier. The proposed architecture uses an integral sliding mode controller with a novel on-chip continuous current sensor. A full-bridge output stage is used to increase the output power, and an adaptive nonoverlapping-clock generation technique is presented to eliminate the short circuit current. Moreover, the switching frequency is chosen to achieve the highest possible linearity without efficiency degradation. The proposed architecture contains the minimum number of loop amplifiers to reduce quiescent current consumption. The proposed class-D audio amplifier has been implemented using 65-nm CMOS technology and operated from a single 2.7-V voltage supply (using thick oxide transistors) while occupying an active area of 0.31 mm2. Post-layout simulations show that the proposed architecture achieves a total harmonic distortion of 0.002% for a 2.2 Vpp 1-kHz input signal. It achieves a peak efficiency of 96% and a maximum output power of 400 mW at an 8-Ω differential load.

Novel buck converter architectures for large step-down conversion ratio

Ultra low duty-cycle clock signal is required in buck converters with large step-down voltage conversion ratio. Given the maximum achievable rise and fall time as well as the minimum ON time of the transistors, this sets a maximum limit on the operating frequency. Different buck converter architectures are proposed to achieve the same voltage conversion ratio with a larger duty cycle. Therefore, the constraints on the minimum transistor ON time and the maximum operating frequency are relaxed. The proposed converters are completely independent on mutual coupling and, as a consequence, they do not suffer from any leakage inductance and do not need any protection or clipping circuits. The analysis produces the relation between the duty-cycle and the voltage gain and shows how much the enhancements are. The simulation results confirm the analysis.

A 12-bit, 200MS/s digitally calibrated pipeline ADC with Embedded Sample and Hold

This paper introduces a 12-bit pipeline Analog to Digital Converter (ADC) using 1.2V and 0.13μm CMOS technology. The first stage utilizes the Embedded Sample and Hold technique to eliminate the dedicated power hungry Sample and Hold circuit. Low gain Opamps are used with a Foreground Digital Calibration scheme to account for the Opamps finite gain and non-linearity. The ADC consumes 65 mW and achieves a maximum SNDR of 68.5 dB with an SFDR up to 80 dB which corresponds to a Figure of Merit (FOM) of about 160 fJ/step.

A sub-2dB noise figure, 200–3700 MHz receiver for LTE-A applications

A wideband low-noise amplifier (LNA) with an inherent active-balun and a wideband Downconversion Mixer are proposed in this work. For the LNA, a combination of a common-gate (CG) stage and a common-source (CS) stage is used to acquire the differential output signal out of a single-ended input while still maintaining acceptable output balancing. A positive feedback loop is added to increase the degree of freedom in choosing the design parameters. This leads to decreasing the overall noise figure (NF) without affecting the input matching performance. The LNA shows a NF below 1.86dB, gain of 25.9dB, and IIP3 of -8dBm across all band (200-3700 MHz). A minimum NF of 1.75dB was achieved at 400-1500 MHz band. For the Mixer, A dual current bleeding technique is used to maintain the linear operation at high input amplitudes to achieve high linearity reaching a maximum IIP3 value of 9.66dBm. The Mixer shows a NF of 13dB and gain 6dB. The front-end is designed in 0.13μm standard CMOS process. A total minimum NF of 1.9dB was achieved with a gain of 31.9dB.