Nikos Kanistras

An encoding scheme and encoder architecture for rate-compatible QC-LDPC codes

We consider the problem of rate-compatible (RC)-encoder and RC-puncturing of LDPC codes. The proposed encoder is based on a modification of MacKay encoding scheme. The introduced modification enables the application of MacKay scheme for quasi-cyclic (QC) LDPC codes combined with a proposed matrix puncturing scheme based on an also proposed parity-check matrix construction to achieve code-rate compatibility. The proposed encoding scheme and VLSI encoder architecture address the problem of encoding complexity, since about 80% of MacKay encoding algorithm complexity is linearly depended on LDPC check node degree. The proposed matrix puncturing scheme can produce good BER performance especially for high puncturing rates, where only a few parity check symbols are transmitted. A comparison with prior art in puncturing is offered, which shows superior performance of the proposed scheme, in terms of coding gain without any hardware cost.

Multiple LDPC decoder of very low bit-error rate

The error correcting capability of LDPC based systems at low noise levels is often dominated by the so-called error floor, a region in the BER vs. noise level plot, where BER reduction slows down as the noise level decreases. The error floor behavior is commonly attributed to the sub-optimality of iterative decoding algorithms on graphs with cycles, which become trapped to local minimum solutions. Trapping of the decoder depends on several factors, including the decoding algorithm. A particular received word that is not decoded by a certain algorithm may be decoded successfully by a different algorithm. The proposed Multiple Decoder exploits this diverse behavior, by decoding a particular received word with N different algorithms, composing an LDPC decoder that achieves very low BER in the error floor region of operation, less iterations and higher throughput than the equivalent single decoder system.

Digital baseband challenges for a 60GHz gigabit link

This paper presents the algorithms and corresponding hardware architectures developed in the context of the nexgen miliwave project, that compose the digital baseband processor of a 60GHz point-to-point link. The nexgen baseband processor provides all basic functionality required from a digital transmitter and receiver, including filtering, synchronization, equalization, and error correction. The techniques selected are capable of compensating impairments due to millimeter-wave front-end and yet support a throughput rate of more than one Gbp, with moderate hardware cost. As the nexgen link targets backhauling applications, a particularly low bit error rate specification of 10−12 has been adopted. Meeting the particular specification, as well as performance and complexity constraints, requires the adoption of sophisticated FEC techniques. Furthermore, extensive verification tasks need to be adopted which include hardware prototyping.

Impact of LLR saturation and quantization on LDPC min-sum decoders

In this paper we quantify the power of noise due to quantization and saturation of the LLRs. Subsequently a model is constructed using the obtained noise power expressions that can be used to estimate the performance of various LLR quantization schemes. The model is validated by comparing the estimation with experimental BER results for an LDPC-based system that uses the min-sum layered decoding algorithm.

A syndrome-based LDPC decoder with very low error floor

This work improves the performance of LDPC decoders that implement iterative algorithms dominated by oscillatory behavior - such as offset Min-Sum algorithm - in cases of unsuccessful decoding of received words. The proposed LDPC decoder is applied on the decoding procedure of an LDPC algorithm by selecting the one of the N different estimated codewords (each produced at an iteration of the decoder) that corresponds to the syndrome with the minimum number of unsatisfied check constraints, as the output of the decoder. This method provides a decoder that achieves a notable performance improvement in the error floor region of operation for the offset Min-Sum decoding algorithm, with an insignificant increase of the hardware complexity.

An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems

This paper introduces a methodology for forward error correction (FEC) architectures prototyping, oriented to system verification and characterization. A complete design flow is described, which satisfies the requirement for error-free hardware design and acceleration of FEC simulations. FPGA devices give the designer the ability to observe rare events, due to tremendous speed-up of FEC operations. A Matlab-based system assists the investigation of the impact of very rare decoding failure events on the FEC system performance and the finding of solutions which aim to parameters optimization and BER performance improvement of LDPC codes in the error floor region. Furthermore, the development of an embedded system, which offers remote access to the system under test and verification process automation, is explored. The presented here prototyping approach exploits the high-processing speed of FPGA-based emulators and the observability and usability of software-based models.

Propagation of LLR Saturation and Quantization Error in LDPC Min-Sum Iterative Decoding

In this paper we investigate the propagation in the decoding procedure of the error due to the finite-word-length representation of the LLRs, for the case of LDPC codes. A model is developed that quantifies the impact of the quantization error of the LLRs on the decoding performance, in case of iterative decoding using the Min-Sum algorithm. An older model, also developed by the authors, exploits the new one in order to estimate the performance of various LLR quantization schemes. Proposed model estimation is compared with experimental BER results, in order to be validated.

Impact of Approximation Error on the Decisions of LDPC Decoding

In this paper the impact of the approximation error on the decisions taken by LDPC decoders is studied. In particular, we analyze the mechanism, by means of which approximation error alters the decisions of a finite-word-length implementation of the decoding algorithm, with respect to the decisions taken by the infinite precision case, approximated here by double-precision floating-point. We focus on four popular algorithms for LDPC decoding, namely Log Sum-Product, Min-Sum, normalized Min-Sum and offset Min-Sum. A corresponding theoretical model is developed which derives an expression for the probability of altering the decision due to approximation. The model is applied to the above algorithms for the case of the first iteration as well as for higher numbers of iterations. Finally, experimental results prove the validity of the proposed model.

Impact of roundoff error on the decisions of the Log Sum-Product algorithm for LDPC decoding

In this paper the impact of the roundoff error on the decisions taken by the log sum-product LDPC decoding algorithm is studied. The mechanism, by means of which roundoff alters the decisions of a finite word length implementation of the algorithm compared to the infinite precision case, is analyzed and a corresponding theoretical model is developed. Experimental results prove the validity of the proposed model.

Impact of roundoff errors in LDPC decoding

In this paper the impact of roundoff mechanisms on the performance of message-passing LDPC decoding is studied. It is shown that finite word length introduces error by means of two mechanisms, each of which is analyzed. The impact and behavior of the two mechanisms are clarified by experimental results.