I. Tsatsaragkos

A flexible layered LDPC decoder

We introduce a flexible layered decoder architecture for Quasi-Cyclic Low Density Parity Check (LDPC) codes. An iterative construction of the parity check matrix is exploited by the proposed decoder to achieve various degrees of parallelism, characterized by a high utilization of variable and check processing nodes, absence of memory conflicts, and a simple and scalable interconnection network. Furthermore, the proposed LDPC decoder supports variable code rate, information-word length and order of modulation. A comparison to prior-art decoders proves the efficiency of the proposed scheme.

Multiple LDPC decoder of very low bit-error rate

The error correcting capability of LDPC based systems at low noise levels is often dominated by the so-called error floor, a region in the BER vs. noise level plot, where BER reduction slows down as the noise level decreases. The error floor behavior is commonly attributed to the sub-optimality of iterative decoding algorithms on graphs with cycles, which become trapped to local minimum solutions. Trapping of the decoder depends on several factors, including the decoding algorithm. A particular received word that is not decoded by a certain algorithm may be decoded successfully by a different algorithm. The proposed Multiple Decoder exploits this diverse behavior, by decoding a particular received word with N different algorithms, composing an LDPC decoder that achieves very low BER in the error floor region of operation, less iterations and higher throughput than the equivalent single decoder system.

Digital baseband challenges for a 60GHz gigabit link

This paper presents the algorithms and corresponding hardware architectures developed in the context of the nexgen miliwave project, that compose the digital baseband processor of a 60GHz point-to-point link. The nexgen baseband processor provides all basic functionality required from a digital transmitter and receiver, including filtering, synchronization, equalization, and error correction. The techniques selected are capable of compensating impairments due to millimeter-wave front-end and yet support a throughput rate of more than one Gbp, with moderate hardware cost. As the nexgen link targets backhauling applications, a particularly low bit error rate specification of 10−12 has been adopted. Meeting the particular specification, as well as performance and complexity constraints, requires the adoption of sophisticated FEC techniques. Furthermore, extensive verification tasks need to be adopted which include hardware prototyping.

Impact of LLR saturation and quantization on LDPC min-sum decoders

In this paper we quantify the power of noise due to quantization and saturation of the LLRs. Subsequently a model is constructed using the obtained noise power expressions that can be used to estimate the performance of various LLR quantization schemes. The model is validated by comparing the estimation with experimental BER results for an LDPC-based system that uses the min-sum layered decoding algorithm.

A syndrome-based LDPC decoder with very low error floor

This work improves the performance of LDPC decoders that implement iterative algorithms dominated by oscillatory behavior - such as offset Min-Sum algorithm - in cases of unsuccessful decoding of received words. The proposed LDPC decoder is applied on the decoding procedure of an LDPC algorithm by selecting the one of the N different estimated codewords (each produced at an iteration of the decoder) that corresponds to the syndrome with the minimum number of unsatisfied check constraints, as the output of the decoder. This method provides a decoder that achieves a notable performance improvement in the error floor region of operation for the offset Min-Sum decoding algorithm, with an insignificant increase of the hardware complexity.

Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation

This brief introduces algorithms and corresponding circuits that identify minimum values among a set of incoming messages. The problem of finding two minima in a set of messages is approximated by the different problem of finding the minimum of all messages in the set and the second minimum among a subset of the messages. This approximation is here shown to be suitable for hardware low-density parity-check decoders that implement a min-sum (MS) decoding algorithm and its variations. The introduced approximation simplifies the operation performed in a check-node processor and leads to hardware reduction. The proposed schemes outperform other state-of-the-art simplified MS architectures, approaching the error-corrective performance of the normalized MS decoding algorithm.

An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems

This paper introduces a methodology for forward error correction (FEC) architectures prototyping, oriented to system verification and characterization. A complete design flow is described, which satisfies the requirement for error-free hardware design and acceleration of FEC simulations. FPGA devices give the designer the ability to observe rare events, due to tremendous speed-up of FEC operations. A Matlab-based system assists the investigation of the impact of very rare decoding failure events on the FEC system performance and the finding of solutions which aim to parameters optimization and BER performance improvement of LDPC codes in the error floor region. Furthermore, the development of an embedded system, which offers remote access to the system under test and verification process automation, is explored. The presented here prototyping approach exploits the high-processing speed of FPGA-based emulators and the observability and usability of software-based models.

Propagation of LLR Saturation and Quantization Error in LDPC Min-Sum Iterative Decoding

In this paper we investigate the propagation in the decoding procedure of the error due to the finite-word-length representation of the LLRs, for the case of LDPC codes. A model is developed that quantifies the impact of the quantization error of the LLRs on the decoding performance, in case of iterative decoding using the Min-Sum algorithm. An older model, also developed by the authors, exploits the new one in order to estimate the performance of various LLR quantization schemes. Proposed model estimation is compared with experimental BER results, in order to be validated.

A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications

This paper presents a high data-rate low-density parity-check (LDPC) decoder, suitable for the 802.11n/ac (WiFi) standard. The innovative features of the proposed decoder relate to the decoding algorithms and the interconnection between the processing elements. The reduction of the hardware complexity of decoders based on the min-sum (MS) algorithms comes at the cost of performance degradation, especially at high-noise regions. We introduce more accurate approximations of the log-sum-product algorithm that also operate well for low signal-to-noise ratio values. Telecommunication standards, including WiFi, support more than one quasi-cyclic LDPC codes of different characteristics, such as codeword length and code rate. A proposed design technique derives networks, capable of supporting a variety of codes and efficiently realizing connectivity between a variable number of processing units, with a relatively small hardware overhead over the single-code case. As a demonstration of the proposed technique, we implemented a reconfigurable network based on barrel rotators, suitable for LDPC decoders compatible with WiFi standard. Our approach achieves low complexity and high clock frequency, compared with related prior works. A 90-nm application-specified integrated circuit implementation of the proposed high-parallel WiFi decoder occupies 4.88 mm2 and achieves an information throughput rate of 4.5 Gbit/s at a clock frequency of 555 MHz.

Error Floor Compensation for LDPC Codes Using Concatenated Schemes

This paper quantitatively investigates the trade-offs in the compensation of error floor on iterative decoders. The characterization of iterative decoding systems prone to error floor at low noise is a great challenge as techniques based on software simulation are inadequate due to the extremely long simulation time required. We compare the BER performance as measured at very low BER using hardware accelerators and study the cost of compensation techniques in terms of hardware complexity and throughput. Specifically, techniques based on the use of diversity in LDPC decoders and the use of concatenated BCH-LDPC codes are considered and corresponding hardware optimizations are discussed. It is shown that an introduced synergy of error-floor compensation techniques achieves substantial coding gain up to 1 dB at low noise, not possible by conventional LDPC or BCH decoders. In addition, hardware reductions are achieved in the BCH subsystem, due to simple post-processing in the LDPC decoder.