Ahmed R. Fridi

A quad-band GSM-GPRS transmitter with digital auto-calibration

A low-power low-voltage fully integrated fast-locking quad-band (850/900/1800/1900-MHz) GSM-GPRS transmitter is described. It exploits closed-loop phase-locked loop (PLL) upconversion using a modulated fractional-N frequency synthesizer with digital auto-calibration. It uses a type-I PLL in a mostly digital IC with no external components and achieves a lock time of 43 /spl mu/s, a tuning range of 500 MHz, receive-band phase noise of -158dBc/Hz and -165 dBc/Hz for the high and low bands, respectively, and reference feed through of -93.9 dBc. It is implemented in 2.1 mm/sup 2/ using a 0.13-/spl mu/m CMOS process and meets all quad-band GSM transmitter specifications with a current consumption of only 28 mA from a single 1.5-V power supply.

A highly-integrated SiGe BiCMOS WCDMA transmitter IC

A highly-integrated SiGe BiCMOS WCDMA transmitter IC consists of VHF, UHF chains, and synthesizers. At 6 dBm output power, it consumes 79 mA at 2.7 V, with a 5% r.m.s. EVM and -42 dBc ACLR at 5 MHz offset. In-band and receive-band output noise are -128 and -135 Bm/Hz, respectively. Fully integrated PLLs use on-chip VCO tanks and require no off-chip loop filters.

A 1.5V 28mA fully-integrated fast-locking quad-band GSM-GPRS transmitter with digital auto-calibration in 130nm CMOS

A 1.5 V 28 mA quad-band GSM-GPRS transmitter, with digital auto-calibration, is implemented in 2.1 mm/sup 2/, using a 0.13 /spl mu/m CMOS process. It achieves a lock time of 43 /spl mu/s, GSM receive band phase noise of -158 dBc/Hz and -165 dBc/Hz for the high- and low-bands, respectively, and reference feed through less than -95 dBc.