Paul A. Fontaine

A quad-band GSM-GPRS transmitter with digital auto-calibration

A low-power low-voltage fully integrated fast-locking quad-band (850/900/1800/1900-MHz) GSM-GPRS transmitter is described. It exploits closed-loop phase-locked loop (PLL) upconversion using a modulated fractional-N frequency synthesizer with digital auto-calibration. It uses a type-I PLL in a mostly digital IC with no external components and achieves a lock time of 43 /spl mu/s, a tuning range of 500 MHz, receive-band phase noise of -158dBc/Hz and -165 dBc/Hz for the high and low bands, respectively, and reference feed through of -93.9 dBc. It is implemented in 2.1 mm/sup 2/ using a 0.13-/spl mu/m CMOS process and meets all quad-band GSM transmitter specifications with a current consumption of only 28 mA from a single 1.5-V power supply.

A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.

A direct-conversion receiver for the 3G WCDMA standard

A highly integrated direct-conversion receiver that satisfies requirements of the third-generation wide-band code-division multiple-access mobile phone standard is described. The receiver integrated circuit includes the front-end low-noise amplifier, downconversion mixers, baseband variable-gain amplifiers, channel-select filters, and the frequency synthesizer. External components are limited to matching elements required for the low-noise amplifier and the mixers and two passive band-select filters. The receiver is implemented in a SiGe BiCMOS process and consumes a total current of 46 mA from a 2.7-V supply.

A 1.5V 28mA fully-integrated fast-locking quad-band GSM-GPRS transmitter with digital auto-calibration in 130nm CMOS

A 1.5 V 28 mA quad-band GSM-GPRS transmitter, with digital auto-calibration, is implemented in 2.1 mm/sup 2/, using a 0.13 /spl mu/m CMOS process. It achieves a lock time of 43 /spl mu/s, GSM receive band phase noise of -158 dBc/Hz and -165 dBc/Hz for the high- and low-bands, respectively, and reference feed through less than -95 dBc.

Multi-mode, multi-band RF transceiver circuits for mobile terminals in deep-submicron CMOS processes

Circuit design techniques, architectures and characterization results for RF and analog circuits for multi-mode, multi-band single-chip RF transceivers are presented. Critical RF and analog design parameters are derived for direct conversion multi-mode transceivers based on UMTS and GSM/DCS/PCS standards. Discrete component specifications are derived based on the linearity and noise figure of the channel. A wideband, high dynamic range continuous-time baseband /spl Sigma//spl Delta/ A/D converter, for fully integrated direct-conversion RF transceivers is presented. RF frequency synthesizers with multi-band VCOs, spanning more than 500 MHz center frequency range, and with low phase noise, are introduced.

A direct conversion receiver for the 3G WCDMA standard

A highly integrated direct-conversion receiver that satisfies requirements of the third generation Wideband Code Division Multiple Access (WCDMA) mobile phone standard is described. The receiver IC includes the front-end low-noise amplifier, down-conversion mixers, channel select filters, baseband variable gain amplifiers, and the entire frequency synthesizer, including the voltage controlled oscillator, buffers and phase-locked loop.