Ajith Amerasekera

The impact of technology scaling on ESD robustness and protection circuit design

The trends in ESD robustness as a function of technology scaling, for feature sizes down to 0.25 /spl mu/m, have been experimentally determined using single finger nMOS transistors and full ESD protection circuits. It is shown that as feature sizes are reduced, good ESD performance can be obtained provided the negative effects of the shallower junctions are offset by the positive effects of the reduction in the effective channel lengths. Hence, processes and protection circuits with feature sizes as small as 0.25 /spl mu/m can be developed without degrading ESD robustness. >

ESD: a pervasive reliability concern for IC technologies

Several aspects of ESD are described from the point of view of the test, design, product, and reliability engineering. A review of the ESD phenomena along with the test methods, the appropriate on-chip protection techniques, and the impact of process technology advances from CMOS to BiCMOS on the ESD sensitivity of IC protection circuits are presented. The status of understanding in the field of ESD failure physics and the current approaches for modeling are discussed. >

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations

A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.

A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery

A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication. A digital 2-tap FFE and a 5-tap DFE in the RX provide channel compensation. A BER of <10-15 is measured over legacy backplanes with 24dB loss at Nyquist. The power consumption and die area are 330mW and 0.45mm2 per TX/RX pair

Substrate pump NMOS for ESD protection applications

The use of a substrate pump to achieve uniform npn protection in a multi-finger NMOS is reported for advanced CMOS technologies with silicide. The novel feature of this device technique is the implementation of a floating guardring to effectively pump the local substrate of the protection NMOS. SPICE simulations are presented to illustrate the device concept as well as the device design optimization.

Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes

The effect of salicides and the influence of the local substrate potential on ESD performance of deep submicron nMOS transistors have been studied. It is shown that salicidation causes a strong dependence of ESD performance on effective channel length in these devices. Salicides also impact the behavior of the lateral npn parasitic bipolar transistor by affecting the emitter efficiency. A higher local substrate potential has been shown to have a positive impact on ESD performance. Based on these results we have designed and demonstrated a substrate triggered nMOS protection circuit which provides >2 kV ESD performance in a fully salicided process.

High-current failure model for VLSI interconnects under short-pulse stress conditions

Short-time high joule heating causing thermal breakdown of metal interconnects in ESD/EOS protection circuits and I/O buffers has become a reliability concern. Such failures occur frequently during testing for latchup robustness and during ESD/EOS type events. In this work, heating and failure of passivated TiN/AlCu/TiN integrated circuit interconnects in a quadruple level metallization system of a sub-0.5 /spl mu/m CMOS technology has been characterized under high-current pulse conditions. A model incorporating the heating of the layered metal system and the oxide surrounding it has been developed which relates the maximum allowable current density to the pulse width. The model is shown to be in excellent agreement with experimental results and is applied to generate design guidelines for ESD/EOS and I/O buffer interconnects.

Self-heating effects in basic semiconductor structures

Investigates the effects of self-heating on the high current I-V characteristics of semiconductor structures using a fully coupled electrothermal device simulator. It is shown that the breakdown in both resistors and diodes is caused by conductivity modulation due to minority carrier generation. In isothermal simulations with T=300 K, avalanche generation is the source of minority carriers. In simulations with self-heating, both avalanche and thermal generation of minority carriers can contribute to the breakdown mechanism. The voltage and current at breakdown are dependent on the structure of the device and the doping concentration in the region with lower doping. For all structures, except highly doped resistors with poor heating sinking at the contacts, the temperature at thermal breakdown ranged from 1.25T/sub i/ to 3T/sub i/, where T/sub i/ is the temperature at which the semiconductor goes intrinsic. Hence, it is found that T=T/sub i/ is not a general condition for thermal (or second) breakdown. From these studies, an improved condition for thermal breakdown is proposed. >

The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal

The effect of interconnect scaling and low-k dielectric on the thermal characteristics of interconnect structures has been characterized for the first time under DC and pulsed current conditions. It is shown that under DC conditions the thermal impedance of metal lines increases by about 10% when low-k dielectric is used as the gap fill. The critical current density for the low-k structures under pulsed condition is shown to be about 10-30% lower than that of standard dielectric structures depending on metal and pulse widths.

Electrothermal behavior of deep submicron nMOS transistors under high current snapback (ESD/EOS) conditions

We present the underlying mechanisms of second breakdown in deep submicron nMOS transistors under high current snapback conditions. The onset of second breakdown is shown to be determined by a rapid increase in the thermally generated component of the substrate (base) current. Simplified simulation methodologies for evaluating high current robustness using isothermal device simulations are demonstrated and good correlations with experimental data have been obtained.<<ETX>>