Mark S. Rodder

Scaled CMOS technologies with low sheet resistance at 0.06-μm gate lengths

A novel Ti self-aligned silicide (salicide) process using a combination of low dose molybdenum and preamorphization (PAI) implants and a single rapid-thermal-processing (RTP) step is presented, and shown to be the first Ti salicide process to achieve low sheet resistance at ultrashort 0.06-/spl mu/m gate lengths (mean=5.2 /spl Omega//sq, max=5.7 /spl Omega//sq at 0.07 /spl mu/m; mean=6.7 /spl Omega//sq, max=8.1 /spl Omega//sq at 0.06 /spl mu/m, TiSi/sub 2/ thickness on S/D=38 nm), in contrast with previous Ti salicide processes which failed below 0.10 /spl mu/m. The process was successfully implemented into a 1.5 V, 0.12-/spl mu/m CMOS technology achieving excellent drive currents (723 and 312 /spl mu/A//spl mu/m at I/sub OFF/=1 nA//spl mu/m for nMOS and pMOS, respectively).

Lower limits of line resistance in nanocrystalline back end of line Cu interconnects

The strong non-linear increase in the Cu interconnect line resistance with decreasing linewidth presents a significant obstacle to their continued downscaling. In this letter we use the first principles density functional theory based electronic structure of Cu interconnects to find the lower limits of their line resistance for metal linewidths corresponding to future technology nodes. We find that even in the absence of scattering due to grain boundaries, edge roughness or interfaces, quantum confinement causes a severe increase in the line resistance of Cu. We also find that when the simplest scattering mechanism in the grain boundary scattering dominated limit is added to otherwise coherent electronic transmission in monocrystalline nanowires, the lower limit of line resistance is significantly higher than projected roadmap requirements in the International Technology Roadmap for Semiconductors.

A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond

A novel tensile Si (tSi) and compressive SiGe (cSiGe) dual-channel FinFET CMOS co-integration scheme, aimed at logic applications for the 5nm technology node and beyond, is demonstrated for the first time, showing electrical performance benefits and excellent co-integration feasibility. A Strain-Relaxed SiGe Buffer (SRB) layer is introduced as buried stressor and successfully transfers up to ∼1 GPa uniaxial tensile and compressive stress to the Si/SiGe n-/p-channels simultaneously. As the result, both tSi and cSiGe devices show a 40% and 10% electron and hole mobility gain over unstrained Si, respectively. Through a novel gate stack solution including a common interfacial layer (IL), HK, and single metal gate for both n- and pFET, secured process margin for 5nm gate length, low interface trap density (Dit) for SiGe channel and threshold voltage (Vt) target for both the Si and SiGe device are successfully demonstrated. Lastly, reliability investigation shows that tSi and cSiGe, employing the newly developed common gate stack scheme, possess superior reliability characteristics compared with those of equivalent Si devices.

Band-to-Band Tunneling in Ge-Rich SiGe Devices

Germanium is one of the promising materials for future CMOS technologies, due to its high carrier mobility and low Schottky barrier height (for PMOS). However, the presence of a small direct gap (in addition to the main indirect gap at the L-point) can result in significant band-to-band tunneling (BTBT), even at low voltages. If not remedied, it is easily the dominant BTBT mechanism. In this letter, the dependence of BTBT on the alloy composition in Ge-rich SiGe is studied using detailed simulation of the bandstructure. It is shown that even a very low stoichiometric fraction of Si in a FinFET results in a dramatic reduction of direct BTBT, much more so than in a corresponding p-i-n diode.

A crystalline oxide passivation on In0.53Ga0.47As (100)

The passivation of In0.53Ga0.47As surfaces is highly desired for transistor performance. In this study, the feasibility of a crystalline oxide passivation on In0.53Ga0.47As (100) is demonstrated experimentally. The (3u2009×u20091) and (3u2009×u20092) crystalline oxide reconstructions are formed on the de-capped In0.53Ga0.47As (100) surfaces through the control of the surface oxidation states. By monitoring the evolution of chemical states and associated structures of the In0.53Ga0.47As (100) surfaces upon O2 and subsequent atomic hydrogen exposure, we find that the control of the Ga oxide states is critical to the formation of the crystalline oxide reconstructions. The stability of the crystalline oxide layers upon the atomic layer deposition of HfO2 is investigated as well. Furthermore, the capacitance voltage behavior of metal oxide semiconductor capacitors with an HfO2 dielectric layer reveals that the crystalline oxide reconstructions result in a decrease in the density of interface traps (Dit) from ∼1u2009×u20091013u2009cm−2u2009eV...

In situ surface and interface study of crystalline (3×1)-O on InAs

The oxidation behavior of de-capped InAs (100) exposed to O2 gas at different temperatures is investigated in situ with high resolution of monochromatic x-ray photoelectron spectroscopy and low energy electron diffraction. The oxide chemical states and structure change dramatically with the substrate temperature. A (3u2009×u20091) crystalline oxide layer on InAs is generated in a temperature range of 290–330u2009°C with a coexistence of In2O and As2O3. The stability of the crystalline oxide upon the atomic layer deposition (ALD) of HfO2 is studied as well. It is found that the generated (3u2009×u20091) crystalline oxide is stable upon ALD HfO2 growth at 100u2009°C.

Is electron transport in nanocrystalline Cu interconnects surface dominated or grain boundary dominated

Through controlled numerical experiments using first principles density functional theory based electron transport, we find that surface effects can dominate electron transport in nanocrystalline Cu interconnects, even in transport regimes that have been interpreted as grain boundary dominated. We find that the role of the surface relative to that of the grain boundaries is sensitive to the degree of Grain Orientation Anisotropy. The implications for interconnect resistance engineering are also discussed.

On the validity and applicability of models of negative capacitance and implications for MOS applications

The observation of room temperature sub-60 mV/dec subthreshold slope (SS) in MOSFETs with ferroelectric (FE) layers in the gate stacks or in series with the gate has attracted much attention. Recently, we modeled this effect in the framework of a FE polarization switching model. However, there is a large amount of literature attributing this effect to a stabilization of quasi-static (QS) negative capacitance (NC) in the FE. The technological implications of a stabilized non-switching (NS) QSNC model vs a FE switching model are vastly different; the latter precluding applications to sub-60 mV/dec SS scaled CMOS due to speed limitations and power dissipated in switching. In this letter, we provide a thorough analysis assessing the foundations of models of QSNC, identifying which specific assumptions (ansatz) may be unlikely or unphysical, and analyzing their applicability. We show that it is not reasonable to expect QSNC for two separate capacitors connected in series (with a metal plate between dielectric (DE) and FE layers). We propose a model clarifying under which conditions a QS apparent NC for a FE layer in a FE-DE bi-layer stack may be observed, quantifying the requirements of strong interface polarization coupling in addition to capacitance matching. In this regime, our model suggests the FE layer does not behave as a NC layer, simply, the coupling leads to both the DE and FE behaving as high-k DE with similar permittivities. This may be useful for scaled EOT devices but does not lead to sub-60 mV/dec SS.

A New Direction for III–V FETs for Mobile CPU Operation Including Burst-Mode: In 0.35 Ga 0.65 As Channel

In this letter, we show that conventional III–V MOSFETs with moderate/high In content channels (In_0.53Ga_0.47As or In_0.70Ga_0.30As) at scaled nodes are incompatible with mobile SoC designs, which often operate at intermediate/high <inline-formula> <tex-math notation=LaTeX>

Modulation of the Schottky barrier height for advanced contact schemes

{V_{{mathrm {dd}}}}