Sridhar Ramaswamy

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations

A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.

A comparison of numerical solutions of the Boltzmann transport equation for high-energy electron transport silicon

In this work we have undertaken a comparison of several previously reported computer codes which solve the semiclassical Boltzmann equation for electron transport in silicon. Most of the codes are based on the Monte Carlo particle technique, and have been used here to calculate a relatively simple set of transport characteristics, such as the average electron energy. The results have been contributed by researchers from Japan, Europe, and the United States, and the results were subsequently collected by an independent observer. Although the computed data vary widely, depending on the models and input parameters which are used, they provide for the first time a quantitative (though not comprehensive) comparison of Boltzmann Equation solutions. >

An improved hydrodynamic transport model for silicon

A closed set of hydrodynamic equations for silicon device analysis is obtained with the aid of self-consistent Monte Carlo device simulation data. This set of macroscopic equations is derived without invoking any phenomenological relations such as the Fourier law for heat flow and the Wiedemann-Franz law for thermal conductivity. The model is developed by taking the first four moments of the Boltzmann transport equation (BTE). This model taken into account the difference between the moments of the collision terms of the BTE both for bulk and inhomogeneous systems. The cause of the spurious velocity overshoot sometimes predicted by other models is identified. By introducing different levels of approximation, this system of hydrodynamic equations can be reduced to the conventional hydrodynamic or energy transport equations. The improved model appears to be more accurate than any existing approach for modeling silicon devices. >

Heat flow analysis for EOS/ESD protection device design in SOI technology

Power-to-failure versus time-to-failure profiles for SOI protection devices are generated through a consideration of Joule heating. Experimental results are presented to justify assumptions made in the investigation of heat flow in SOI devices. A lossy transmission line equivalent model has been used to model the heat diffusion problem. A design space for multifinger NMOS protection devices has been developed on the basis of self-heating constraints. The method of images has been used to transform the multifinger device to an equivalent single-finger device to simplify the heat flow analysis.

EOS/ESD reliability of deep sub-micron NMOS protection devices

We have identified new failure mechanisms in EOS/ESD protection circuits for a 0.35 /spl mu/m technology and investigated the effect of process variations on these circuits. We present strategies to improve the performance of these circuits and prevent premature failure of the devices.

EOS/ESD protection circuit design for deep submicron SOI technology

Deep submicron silicon-on-insulator (SOI) is potentially an important technology for low voltage applications because of advantages in processing, speed, subthreshold conduction and latchup immunity. However, little attention has been given to EOS/ESD protection circuit design issues for submicron SOI technology. Multi-finger grounded gate NMOS (GGNMOS) devices have been used as effective output protection devices for bulk Si technology. In this paper, we investigate the failure modes of GGNMOS devices designed for a 0.3 /spl mu/m fully depleted SOI technology. We provide a theoretical comparison between the EOS/ESD performance of bulk and SOI technologies. We also provide practical design guidelines for effective protection circuit design in SOI technology.

Comparison of semiconductor transport models using a Monte Carlo consistency test

This paper proposes a scheme to compare different transport models which are used to simulate submicron semiconductor devices. The procedure requires self-consistent Monte Carlo simulation data for a particular test device. We have compared four different hydrodynamic transport models which have been proposed recently. All four sets of hydrodynamic equations can be cast into a single form by selecting appropriate models for various transport parameters. The advantage is that we can use the same discretized set of equations to implement different transport models. We have also compared the results obtained from the Monte Carlo consistency test with those obtained by the hydrodynamic equation solver. The consistency test has been used to highlight the merits and demerits of the transport models on a common platform. >

Study of a CMOS I/O protection circuit using circuit-level simulation

In this work, circuit-level simulation is conducted for a typical two-stage protection circuit. We demonstrate that the circuit failure mechanism is correctly predicted by simulation. Furthermore, the current protection levels estimated by simulation are in good agreement with the experiments; therefore, circuit-level simulation can be used to predict the HBM-ESD protection level. In addition, the failure site is explained by simulation.

Circuit-level simulation and layout optimization for deep submicron EOS/ESD output protection device

This work presents circuit-level simulation and layout optimization techniques for a multifinger NMOS device. By considering the full thermal-coupling of heat sources at each drain finger, simulations reflect the device layout dependent behavior in silicon under EOS/ESD. Simulation reveals that each NMOS finger may carry a different stress current due to the non-symmetrical heat-coupling effect; as a result, the effective total NMOS width will be reduced. Simulation results agree well with the measured data. We also propose a design and layout optimization methodology which is illustrated with a design example.

Circuit-level electrothermal simulation techniques for designing output protection devices

The design of I/O protection circuits is crucial for the reliable operation of integrated circuits. Typical protection circuits are designed to meet certain specifications (ESD/EOS failure levels) and the use of CAD tools in the design stage will help in their characterization and design. We recently developed a circuit-level electrothermal simulator, iETSIM, which we have used to study different protection circuit designs. iETSIM solves the heat diffusion equation simultaneously with the device electrical equations. The device models extend to the avalanche breakdown regime. We show that the circuit-level electrothermal simulator can be a useful tool for designing reliable output protection devices.