Jerold A. Seitchik

Self-heating effects in basic semiconductor structures

Investigates the effects of self-heating on the high current I-V characteristics of semiconductor structures using a fully coupled electrothermal device simulator. It is shown that the breakdown in both resistors and diodes is caused by conductivity modulation due to minority carrier generation. In isothermal simulations with T=300 K, avalanche generation is the source of minority carriers. In simulations with self-heating, both avalanche and thermal generation of minority carriers can contribute to the breakdown mechanism. The voltage and current at breakdown are dependent on the structure of the device and the doping concentration in the region with lower doping. For all structures, except highly doped resistors with poor heating sinking at the contacts, the temperature at thermal breakdown ranged from 1.25T/sub i/ to 3T/sub i/, where T/sub i/ is the temperature at which the semiconductor goes intrinsic. Hence, it is found that T=T/sub i/ is not a general condition for thermal (or second) breakdown. From these studies, an improved condition for thermal breakdown is proposed. >

Electrothermal behavior of deep submicron nMOS transistors under high current snapback (ESD/EOS) conditions

We present the underlying mechanisms of second breakdown in deep submicron nMOS transistors under high current snapback conditions. The onset of second breakdown is shown to be determined by a rapid increase in the thermally generated component of the substrate (base) current. Simplified simulation methodologies for evaluating high current robustness using isothermal device simulations are demonstrated and good correlations with experimental data have been obtained.<<ETX>>

An accurate bipolar model for large signal transient and ac applications

It is shown that models employing only two ac parameters can be accurate, at best, to first order in frequency. A new small signal model is presented, and it is demonstrated by comparison with exact results that only three ac parameters are sufficient to maintain model accuracy at much higher frequencies than achieved by any previous model. (At and below the unity gain frequency, ωT, the maximum magnitude error is 2% and the maximum phase error is 1.1°.) Analytic expressions are given for the 3 parameters. The validity of the charge sharing scheme of Ref. 1 is established. A large signal model is presented which can be easily and efficiently incorporated into the existing SPICE Gummel-Poon model.

IVB-6 alpha-particle-induced charge transfer between closely spaced memory cells

A detailed analysis of various mechanisms involved in α-particle-induced charge transfer between two trench-type DRAM cells is reported. An analytical model has been developed to describe the charge-transfer mechanisms. The charge-collection process consists of two phases. In the first phase, funneling is tile dominant mechanism, and the axial current is calculated based on the drift component. In the second phase, the structure behaves similarly to a bipolar transistor, and both the drift and diffusion components contribute to the charge transfer. A discussion of the dependence of the charge transfer on stored charge, cell separation, charge in the α-particle track, and the substrate doping concentration is presented.

Comments, with reply, on "One-dimensional non-quasi-static models for arbitrarily and heavily doped quasi-neutral layers in bipolar transistors" by B. Wu and F. Lindholm

For original paper see ibid., vol.36, pp.727-37 (April 1989). The accuracy of state-of-the-art AC models for the emitter and base of bipolar transistors is examined in order to clear up some confusion that the commenter believes results from original paper concerning the distinctions between a base transport model and that of J. Seitchik et al. (see IEDM Tech. Dig., pp.244-7, 1987). The authors respond with further discussion of emitter-transport and base-transport models and concede that they may have made mistakes in their comparison with the results of Seitchik et al. >

Single event charge collection modeling in CMOS multi-junctions structure

Simulation was utilized to enable the study of the time dependent carrier and potential distributions that occur following the impact of heavy ion in multi-junction structures associated with CMOS technology. These simulations reveal a charge collection process which is quite complex However, the process can be more readily understood in it is broken into phases in which only a few mechanisms dominate the overall behavior. These phases, denoted the funneling phase and bipolar phase, can be represented by simple analytic models. The quantitative predictions of this model are shown to compare well with simulations.

An improved circuit model for CMOS latchup

The traditional n-p-n---p-n-p transistor model for CMOS latchup does not adequately describe the latchup path of modern epitaxial devices, a fact which accounts for its inability to produce satisfactory results for devices having a high holding voltage. In this letter a more physically based equivalent circuit representation is discussed. The model better depicts bulk ohmic voltage drops and is more descriptive of the latchup phenomena in epitaxial CMOS devices.

Accurate measurements of small charges collected on junctions from alpha particle strikes using an accelerator-produced microbeam

We describe an accelerator-based system for accurate experiments of alpha particle strikes on integrated circuits. It produces a high-flux, micron-dimensioned collimated beam in air. High speed blanking controls the arrival time and number of alphas. We accurately measure the small alpha-generated charges that collect on junctions using novel test structures and measure SRAM soft error rates. The test structure results are compared to results from our fast alpha-strike simulator.

Transient base dynamics of bipolar transistors in high injection

The transient behavior of a bipolar transistor in high level injection is analyzed both through simulations and an analytic model based on the quasi-neutral base approximation. It is found that, unlike the situation for low injection, transient operation can be influenced by the base majority carrier mobility and by the characteristics of the extrinsic base. While the quasi-neutrality approximation frequently remains valid, cases are presented in which it fails. In these cases, the transient conditions cause at least some small region of the normally quasi-neutral base to develop a space charge. The reclaimable fraction of the stored base charge is determined and discussed. >

Direct evidence supporting the premises of a two-dimensional diode model for the parasitic thyristor in CMOS circuits built on thin epi

A key concept of a recent model to describe the holding point of thyristors in epitaxial CMOS is that due to conductivity modulation, the two-dimensional (2-D) thyristor is equivalent to a p-i-n diode of the same geometry. Here, the physical origin of negative resistance near the holding point is traced to resistance modulation in the epi. This positive feedback mechanism, inherent in the model, is conceptually different from that of the conventional model, in which negative resistance arises out of an increase in the feedback gain as the bipolar transistors come out of saturation. The I-V characteristics of thyristors and p-i-n diodes obtained from PISCES are shown to be almost identical. If the conventional mechanism were solely responsible for the negative resistance region, a thyristor would exhibit negative resistance while a 2-D diode would not. Experimental evidence showing that diodes exhibit negative resistance regions is presented to support the feedback mechanism of the model.<<ETX>>