Ajith Varghese

Material dependence of hydrogen diffusion: implications for NBTI degradation

Negative bias temperature instability (NBTI) is known to exhibit significant recovery upon removal of the gate voltage. The process dependence of this recovery behavior is studied by using the time slope (n) as the monitor. We observe a systematic variation of n with oxide thickness, nitrogen concentration, and fluorine implantation. Incorporation of the material dependence of the diffusivity within the reaction-diffusion (R-D) framework captures the observed trends. The consequences of this modification are (a) diffusion limitation is shown to arise from diffusion in poly-Si, rather than oxide, (b) a plausible explanation for low-voltage stress induced leakage current (LV-SILC) naturally appears. Important findings are (a) NBTI degradation remains significant at high frequencies, (b) numerical simulations at moderate frequencies can be used to predict circuit impact in the GHz regime, (c) high frequency operation can be modeled as a lower effective DC stress

An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

In this abstract we present a highly manufacturable, high performance 90nm technology with best in class performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel stress and implant profile to generate enhanced performance with no additional masks. High drive currents of 1193uA/um and 587uA/um are obtained for nMOS and pMOS transistors respectively at 1.2V Vdd and an Ioff of 60nA//spl mu/m. An industry leading 90nm technology CV/I of 0.61 ps and 1.12ps are obtained for nMOS and pMOS transistors respectively. An aggressively scaled 12/spl Aring/ EOT plasma-nitrided, cluster gate dielectric is used. Process conditions are optimized to obtain high drive current, good Vt roll-off control and simultaneously meet reliability requirements.

Intrinsic reoxidation of microwave plasma-nitrided gate dielectrics

The impact of nitrogen concentration on nitrided gate dielectric scaling has been found to depend on the process conditions used to incorporate nitrogen. For example, the variation in the nitrogen content of gate dielectrics processed at high pressure (>107Pa) has a strong impact on gate leakage current, but not on equivalent oxide thickness. While this effect allows nearly independent control of gate leakage and drive currents of the device, it prevents scaling of the gate dielectric. In contrast, it is found that at low process pressures (<13Pa) the gate dielectric behaves in a more conventional fashion, where both electrical oxide thickness and film leakage change with film nitrogen content. A model is proposed to explain this behavior based on an intrinsic reoxidation process. Chemical bond analysis results are presented to support the proposed model.

A high performance 90 nm logic technology with a 37 nm gate length, dual plasma nitrided gate dielectric and differential offset spacer

A 90 nm logic technology is presented featuring an aggressively scaled 37 nm gate length, 1.3 nm EOT plasma nitrided gate dielectric with differential offset spacer and leading edge CV/I performance. NMOS and PMOS transistors have been optimized with different extension offsets for NMDD and PMDD implants, which enables independent optimization of short channel effects, parasitic capacitance and drive current. The gate dielectric meets reliability requirements at 1.2 V operation. The technology includes a standard Vt (SVt) transistor, low Vt (LVt) transistor and 1.5 V IO transistor with l00 nm gate length and dual plasma nitrided gate dielectric.

Non-contact implant dose and energy metrology for advanced CMOS low-energy implants

Ultra Shallow Junctions are required to successfully improve device performance with scaling to have a better threshold voltage control, improve transistor performance, reduce CHC (Channel Hot Carrier) degradation and reduce parasitic capacitance. All these play an increasingly critical role as we move on to the 45 nm node and beyond to provide the required ac and dc device performance for CMOS devices. In the low energy implant regime, four point probe based sheet resistivity measurement becomes highly unreliable as does silicon damage based metrology systems used currently for advanced process control and monitoring. A non-contact metrology method is investigated based on leakage and tunneling currents in a non-conductive film that contains the implanted dose. These shallow implants damage the non-conductive film causing leakage paths to the silicon substrate. The implant damage is proportional to the dose and energy of the implanted species. Furthermore implanting the non-conductive film causes the top layers of the film to become conductive thus changing the electrical oxide thickness of this film. Excellent correlation was found among the implanted dose, energy to the equivalent oxide thickness. Results from controlled experiments indicate that this method has potential for use in low energy implanter qualification and ultra large scale integration process control and monitoring.

In‐Line Control and Rapid Process Development of Nitrided Gate Oxides

Nitrided gate oxides on Si wafers were investigated by X‐ray Photoelectron Spectroscopy (XPS) and non‐contact surface voltage and surface photovoltage measurements of Corona‐Oxide‐Semiconductor (COS) structures. The XPS measured the physical parameters of N dose and film thickness, while the COS measured the equivalent oxide thickness and a leakage indicator. The XPS N dose, XPS thickness and the COS leakage indicator met the stability, precision, and time dependence requirements for process control, but the COS EOT was unstable possibly due to variations in substrate doping. In lot‐based measurements of 65 nm node wafers, the COS leakage indicator correlated to gate leakage for two different oxide thicknesses with a correlation R2 of 0.85, whereas XPS N dose correlated for only one oxide thickness with a correlation R2 of 0.47. None of the lot‐based measurements correlated to threshold voltage. The suitability of XPS, COS and single wavelength ellipsometry for rapid process development was determined by ...