Akihiko Ohtani

A video digital signal processor with a vector-pipeline architecture

A description is given of a 2-GOPS, 60-MIPS video digital signal processor ULSI with a vector-pipeline architecture for video CODEC systems, called the vector digital signal processor (VDSP). The VDSP uses 0.8- mu m CMOS technology and contains a discrete cosine transform (DCT) core as a special processing unit. The vector-pipeline (VP) architecture allows input vector data to be processed in various pipeline configurations. The VDSP performs motion vector detection, motion compensation, DCT/IDCT, loop filtering, quantization/inverse quantization, and variable length coding/decoding specified in CCIT H.261. The encoder and the decoder specified in the subset including the applications of CCIT H.261 (full-CIF mode at 15 frame/s or more, 64 kb/s) can be realized with only two VDSP chips, and only one VDSP chip, respectively, and thus have twice the performance of prior digital signal processors. >

A 100 mm/sup 2/ 0.95 W single-chip MPEG2 MP@ML video encoder with a 128GOPS motion estimator and a multi-tasking RISC-type controller

A single-chip MPEG2 video encoder, VDSP3, has ten cores. All cores are executed in a macroblock-level pipeline similar to that of a previous LSI, VDSP2. The VIF transfers input video data in MPEG format. The ME1 and ME2 functions form a two-step, motion-estimation process. The MSP calculates statistical values for mode selection. The DCTQ performs the forward and inverse functions for both the DCT and quantization. The VLC outputs MPEG2 video streams. The CIF supports both constant-rate and DMA outputs of PES packets. The ERISC controls each core and is capable of performing rate control. The CLKCTL, with a PLL, supplies clock pulses to each core adaptively. The MSP, DCTQ and VLC are modified VDSP2 cores. By using the VDSP3, an MPEG2 MP@ML video encoder system can be realized with two 16 Mb SDRAMs controlled by the MIF in the VDSP3. Regions for the input image, re-ordering, local decoded image and video bit buffer (VBB) are mapped onto the SDRAMs.