Masaki Toyokura

A video digital signal processor with a vector-pipeline architecture

A description is given of a 2-GOPS, 60-MIPS video digital signal processor ULSI with a vector-pipeline architecture for video CODEC systems, called the vector digital signal processor (VDSP). The VDSP uses 0.8- mu m CMOS technology and contains a discrete cosine transform (DCT) core as a special processing unit. The vector-pipeline (VP) architecture allows input vector data to be processed in various pipeline configurations. The VDSP performs motion vector detection, motion compensation, DCT/IDCT, loop filtering, quantization/inverse quantization, and variable length coding/decoding specified in CCIT H.261. The encoder and the decoder specified in the subset including the applications of CCIT H.261 (full-CIF mode at 15 frame/s or more, 64 kb/s) can be realized with only two VDSP chips, and only one VDSP chip, respectively, and thus have twice the performance of prior digital signal processors. >

Video DSP architecture for MPEG2 codec

We developed a DSP named VDSP2 (Video Digital Signal Processor version 2) for MPEG2 video coding and decoding. In order to obtain the necessary performance, we employed a 2-level parallel processing scheme consisting of a pipeline processing at the macro block level and a parallel vector processing using a SIMD configuration at the block level. In the VDSP2, we included a DSP core which execute 4 parallel vector operations and scalar operations, a DRAM controller, a DCT/IDCT circuit, a VLC/VLD circuit including a programmable controller and a data communication circuit. As a result, the real-time encoder specified in MPEG2 can be realized with two VDSP2 chips, and the decoder can be realized with one VDSP2 chip.<<ETX>>

The architecture of a vector digital signal processor for video coding

Develops a high-performance vector digital signal processor (VDSP) for video coding that can execute instructions at 60 MHz. The VDSP employs a vector pipeline (VP) architecture, which is very well suited for image processing. In the VDSP, a DCT/IDCT circuit (CCITT standard), a two-dimensional space address generator (SAG), and an enhanced ALU to the VP architecture are included, and, as a result, a performance of 2.0 GOPS (giga operation per second) was achieved. The encoder and the decoder specified in CCITT H.261 (Full-CIF mode at 15 frame/s, 64 kb/s) can be realized with two VDSP chips, and one VDSP chip, respectively.<<ETX>>

A 30 ns (600 MOPS) image processor with a reconfigurable pipeline architecture

A 30-ns (600-MOPS) image processor is described. The 200 K-transistor chip has been fabricated in a 1.2-μm CMOS. A reconfigurable pipeline architecture with an array of nine multiplier/accumulators (MAC) is implemented by interchanging its pipelined data paths. This allows it to perform both matrix products and convolutions, systolically, for the discrete cosine transform (DCT) and transversal filters at HDTV rate. 512 by 512-pixel image data can be computed in less than 7.9 ms with sufficient resolution