Kunitoshi Aono

An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput

Nonvolatile memories with fast write operation at low voltage are required as storage devices to exceed flash memory performance. We develop an 8Mb multi-layered cross-point ReRAM macro with 443MB/S write throughput (64b parallel write per 17.2ns cycle), which is almost twice as fast as existing methods, using the fast-switching performance of TaOχ ReRAM and the following three techniques to reduce the sneak current in bipolar type cross-point cell array structure in an 0.18μm process. First, memory cell and array technologies reduce the sneak current with a newly developed bidirectional diode as a memory cell select element for the first time. Second, we use a hierarchical bitline (BL) structure for multi-layered cross-point memory with fast and stable current control. Third, we implement a multi-bit write architecture that realizes fast write operation and suppresses sneak current. This work is applicable to both high-density stand-alone and embedded memory with more stacked memory arrays and/or scaling memory cells.

Demonstration of high-density ReRAM ensuring 10-year retention at 85°C based on a newly developed reliability model

A new oxygen diffusion reliability model for a high-density bipolar ReRAM is developed based on hopping conduction in filaments, which allows statistical predication of activation energy. The filament in the active cells is confirmed by EBAC and TEM directly for the first time. With optimized filament size, a 256-kbit ReRAM with long-term retention exceeding 10 years at 85°C is successfully demonstrated.

A video digital signal processor with a vector-pipeline architecture

A description is given of a 2-GOPS, 60-MIPS video digital signal processor ULSI with a vector-pipeline architecture for video CODEC systems, called the vector digital signal processor (VDSP). The VDSP uses 0.8- mu m CMOS technology and contains a discrete cosine transform (DCT) core as a special processing unit. The vector-pipeline (VP) architecture allows input vector data to be processed in various pipeline configurations. The VDSP performs motion vector detection, motion compensation, DCT/IDCT, loop filtering, quantization/inverse quantization, and variable length coding/decoding specified in CCIT H.261. The encoder and the decoder specified in the subset including the applications of CCIT H.261 (full-CIF mode at 15 frame/s or more, 64 kb/s) can be realized with only two VDSP chips, and only one VDSP chip, respectively, and thus have twice the performance of prior digital signal processors. >

Conductive filament scaling of TaO x bipolar ReRAM for long retention with low current operation

We demonstrate for the first time that the density of oxygen vacancy in a conductive filament plays a key role in ensuring data retention. We achieve very good retention results up to 100 hours at 150°C even under the low current operation due to the scaling of conductive filament size while retaining sufficiently high density of oxygen vacancy.

An image signal multiprocessor on a single chip

A digital image signal multiprocessor (ISMP), a multiprocessor version of a previous real-time image signal processor (RISP) for gray-level image processing, is discussed. It is composed of a main controller and four processor elements (PEs), which are programmable 12-b digital signal processors. One PE has the processing speed of 50-million microinstructions-per-second. The ISMP has 200-million microinstructions-per-second performance using parallel processing with a round-robin method for local image processing. In the other operation mode, each PE processes the same image data with different feature-extracting programs. In addition, system processing power can be easily increased through a novel multichip processing mode. It has 30000 transistors on a 14.4-mm*13.7-mm chip using 1.2- mu m double-metal CMOS process technology. Its power dissipation is 2.9 W. >

Video DSP architecture for MPEG2 codec

We developed a DSP named VDSP2 (Video Digital Signal Processor version 2) for MPEG2 video coding and decoding. In order to obtain the necessary performance, we employed a 2-level parallel processing scheme consisting of a pipeline processing at the macro block level and a parallel vector processing using a SIMD configuration at the block level. In the VDSP2, we included a DSP core which execute 4 parallel vector operations and scalar operations, a DRAM controller, a DCT/IDCT circuit, a VLC/VLD circuit including a programmable controller and a data communication circuit. As a result, the real-time encoder specified in MPEG2 can be realized with two VDSP2 chips, and the decoder can be realized with one VDSP2 chip.<<ETX>>

Filament scaling forming technique and level-verify-write scheme with endurance over 107 cycles in ReRAM

Resistive RAM (ReRAM) has been recently developed for applications that require higher speed and lower voltage than Flash memory is able to provide. One of the applications is micro-controller units (MCUs) or SoCs with several megabits of embedded ReRAM. Another is solid-state drives (SSDs) where a combination of higher-density ReRAM and NAND flash memory would achieve high-performance and high-reliability storage [1], suitable for server applications for future cloud computing. ReRAM is attractive for several reasons. First, it operates at high speed and low voltage. Second, it enables high density due to the simple structure of the resistive element (RE) [2]. Third, it is immune to external environment such as magnetic fields or radiation, since the resistive switching is based on the redox reaction [3].

Retention Model for High-Density ReRAM

A retention model for both the high resistance state and low resistance state of the bipolar ReRAM is developed. Degradation of resistance is caused by the oxygen vacancy profile in filament changing due to oxygen diffusion.

A 100 mm/sup 2/ 0.95 W single-chip MPEG2 MP@ML video encoder with a 128GOPS motion estimator and a multi-tasking RISC-type controller

A single-chip MPEG2 video encoder, VDSP3, has ten cores. All cores are executed in a macroblock-level pipeline similar to that of a previous LSI, VDSP2. The VIF transfers input video data in MPEG format. The ME1 and ME2 functions form a two-step, motion-estimation process. The MSP calculates statistical values for mode selection. The DCTQ performs the forward and inverse functions for both the DCT and quantization. The VLC outputs MPEG2 video streams. The CIF supports both constant-rate and DMA outputs of PES packets. The ERISC controls each core and is capable of performing rate control. The CLKCTL, with a PLL, supplies clock pulses to each core adaptively. The MSP, DCTQ and VLC are modified VDSP2 cores. By using the VDSP3, an MPEG2 MP@ML video encoder system can be realized with two 16 Mb SDRAMs controlled by the MIF in the VDSP3. Regions for the input image, re-ordering, local decoded image and video bit buffer (VBB) are mapped onto the SDRAMs.

The architecture of a vector digital signal processor for video coding

Develops a high-performance vector digital signal processor (VDSP) for video coding that can execute instructions at 60 MHz. The VDSP employs a vector pipeline (VP) architecture, which is very well suited for image processing. In the VDSP, a DCT/IDCT circuit (CCITT standard), a two-dimensional space address generator (SAG), and an enhanced ALU to the VP architecture are included, and, as a result, a performance of 2.0 GOPS (giga operation per second) was achieved. The encoder and the decoder specified in CCITT H.261 (Full-CIF mode at 15 frame/s, 64 kb/s) can be realized with two VDSP chips, and one VDSP chip, respectively.<<ETX>>