Akinori Kanasugi

A wafer-scale 170000-gate FFT processor with built-in test circuits

The wafer-scale 170000-gate fast Fourier transform (FFT) processor described consists of individual repeatable building blocks, each of which contains a processing element (PE) and interconnection wiring. The PE consists of a multiplier accumulator and its built-in self-test circuits. The wafer system is reconfigured by connected active blocks after block self-diagnosis. Blocks are connected using a programmable contact-hole mask. The processor performs parallel 16-bit, eight-point complex FFTs and is implemented with 725 I/O pads in triple-metal 2.3- mu m p-well CMOS technology on a 4-in. wafer. It is mounted by controlled-collapse bonding facedown on a 11.8*11.8-cm/sup 2/ substrate. >

A Design of Architecture for Rough Set Processor

This paper proposes architecture of rough set processor. The theory of rough sets has a lot of applications such as data mining, decision support system, machine learning and so on. However, no specific processor has been developed. In this paper, the architecture of rough set processor is shown.

A wafer-scale FFT processor featuring a repeatable building block

The wafer-scale 170000-gate fast Fourier transform (FFT) processor has three features: a single repeatable building block containing a processing element (PE) and its interconnects, mask-programmable routing by the placement of contact holes, and a built-in self-test (BIST) for the PE and its interconnects. The wafer system is composed of 48 PEs selected out of a total of 88 PEs. The PE consists of a 2800-gate multiplier-accumulator and 700-gate BIST circuitry. The processor performs parallel 16-bit, 8-point complex FFT and is implemented with 725 I/O pads in triple-metal 2.3- mu m CMOS technology on a 4-inch wafer. This wafer is mounted face down on an 11.8*11.8-cm/sup 2/ substrate by solder bumps.<<ETX>>

Design and Implementation of Rough Rules Generation from Logical Rules on FPGA Board

In this paper, the design, simulation, implementation and experiment of rough set processor are described. The experiment result shows that the proposed processor is ten times faster than PC, though the clock frequency is about 70 times lower.

Analysis of pulse propagation on high-T/sub c/ superconducting transmission lines

The propagation characteristics of high-T/sub c/ superconducting microstrip transmission lines are calculated from the viewpoint of interconnection technology. A detailed analysis was made to examine the attenuation and phase velocity of a pulse on a YBCO transmission line, taking into consideration of dielectric loss of the MgO substrate. The results of this analysis are compared with the measured propagation constants of YBCO strip line fabricated on a MgO substrate. It is shown that the effect of dielectric loss of a substrate to the attenuation of a microstrip line is dominant and cannot be neglected as long as a MgO substrate is used. How a pulse propagates on the superconducting transmission line and how the circuit parameters of transmission line affect the propagation characteristics of the line were investigated. Simulation results show that the high-T/sub c/ superconducting transmission lines are more promising for interconnections than the conventional transmission lines by virtue of their lower attenuation and less dispersion, even if a dielectric loss of a MgO substrate is taken into consideration.

A Design and Simulation for Dynamically Reconfigurable Systolic Array

Systolic array is known as an architecture that can process a large amount of data with high speed, by large scale parallel and pipeline processing. If dynamic reconfiguration of systolic array is realized, flexible circuit construction and reduction of circuit scale become possible, without sacrificing the processing speed. Therefore, this paper proposes an architecture of dynamically reconfigurable systolic array (DRSA). The circuit was designed by using VHDL, and verified with a logic circuit simulator. The calculations of matrix such as 1-by-64 and 8-by-8 were simulated correctly with a lot of PEs (Processing Element). The effectiveness of proposed architecture is confirmed by circuit simulation results.

A novel coding method for genetic algorithms based on redundant binary numbers

This article proposes a novel genetic algorithm (GA) which switches the expression of the solution from a redundant binary number to a usual binary number. Furthermore, a GA which switches the expression from the Gray code to the usual binary number is proposed and compared. Comparisons of the performances among five GAs (binary number, redundant binary number, Gray code, switching from redundant binary number to binary number, switching from Gray code to binary number) are illustrated. The performances are evaluated by solving some equations. It is confirmed that the proposed GA effectively decreases the error rate.

Genetic Algorithm that can Dynamically Change Number of Individuals and Accuracy

This paper proposes a novel processor for genetic algorithm (GA) that can dynamically change number of individuals and accuracy. In conventional GA, number of population and accuracy are fixed. However, the accuracy of solution is low at first-half stage. Therefore, the number of population is doubled at expense of the accuracy of solution, and the searching ability is improved at first-stage in the proposed GA processor. Then, the number of population is reduced by half, and the accuracy is improved at second-half stage. As a result, the searching ability is improved. The proposed GA processor was designed by using VHDL and verified. The effectiveness of proposed method was confirmed by applying to the knapsack problem.

A Processor for Genetic Algorithm Based on Redundant Binary Number

A Design and Simulation for DynamicThis paper describes a design of novel processor for genetic algorithm (GA) based on redundant binary number. In conventional GA, genetic information is expressed by binary number. On the other hand, the proposed processor is based on redundant binary number. Therefore, the number of expression of optimized solutions for the target function increase. For this reason, it is easy to find the optimized solution, and error rates decrease. The processor was designed by using VHDL and simulated. The effectiveness of the proposed processor was confirmed by logic circuit simulations.

A Genetic Algorithm for Switchbox Routing Problem

A genetic routing method for switchbox problem with novel coding technique is presented. The principle of proposed method and results of computer experiments are described in detail.