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Featured researches published by Akinori Tahara.


IEEE Transactions on Electron Devices | 1991

Analysis of highly doped collector transistors by using two-dimensional process/device simulation and its application of ECL circuits

Hiroshi Goto; Yoji Nagase; Tadakazu Takada; Akinori Tahara; Yoshinobu Momma

A report is presented of the results of an investigation of device parameters and collector-to-emitter breakdown voltages of double polysilicon self-aligned transistors with highly doped collectors using a two-dimensional process/device simulation system. Favourable phosphorous-ion implanting condition for a highly doped pedestal collector was found to achieve a high cutoff frequency as well as low AC base resistance and small base-collector capacitance, thereby keeping the minimum collector-to-emitter breakdown voltage of 3 V. The authors also report ECL circuit performance improvements achieved in experiments that realized a minimum ECL gate delay time of 26.3 ps/gate at switching current of 1.64 mA as a result of process optimization. Moreover, a 1/8 static frequency divider T-F/F has been observed to operate up to a maximum frequency of 15.8 GHz. >


bipolar circuits and technology meeting | 1989

Low-power high-speed ECL circuit with 0.5- mu m rule and 30-GHz f/sub T/ technology

Akinori Tahara; Kenji Hashimoto; H. Katakura; I. Amano; T. Deguchi; S. Sudo

Optimized self-aligned transistors for low-power ECL (emitter-coupled-logic) circuit applications are discussed. The ECL circuit was fabricated using a 0.5- mu m rule and a 28-GHz f/sub T/ technology and evaluated in terms of the propagation delay time of ring oscillators and a 1/8 static divider. The analysis of the circuit, the process design, and the npn transistor structure are discussed. A 39-ps/1.6-mW ECL circuit and a 12.5-GHz 1/8 static divider were obtained.<<ETX>>


european solid state device research conference | 1992

SiC Growth and Its Application to High-Speed Si-HBTs

T. Sugii; Tatsuya Yamazaki; Yoshihiro Arimoto; Takashi Ito; Yuji Furumura; I. Namura; Hiroshi Goto; Akinori Tahara

This paper discusses the limitations of a conventional poly-Si emitter for sub 0.5μm bipolar transistors and presents a breakthrough using a heterojunction at the emitter-base junction with an SiCx widegap emitter. Both SiCx widegap emitter HBTs and poly-Si emitter transistors with comparable device structures are examined. Low base resistance was achieved using a 1x1019/cm3 base dopant concentration, while retaining an acceptable current gain and suppressing forward-bias tunneling current using the SiCx emitter. A very thin , highly doped base was combined with the SiCx emitter to demonstrate high-speed capability.


Archive | 1992

SiCχ:F Hetero-Emitter and Epitaxial-Base Bipolar Transistors

T. Sugii; Tatsuya Yamazaki; Yoshihiro Arimoto; Takashi Ito; I. Namura; Hiroshi Goto; Akinori Tahara

This paper discusses the technology issues on an emitter and base for sub 0.5 µm bipolar transistors. The new opportunities offered by heterojunction structures and a low-temperature-grown epitaxial base increase the freedom of device design. The SiCx wide-gap emitter with thin, highly doped epitaxial base shows superior characteristics for LSI application owing to the freedom. Low base sheet resistance was achieved using 1×1019 /cm3 concentration base, while retaining an acceptable current gain and suppressing forward-bias tunneling current. We obtained a 30 GHz cutoff frequency for a 35-nm base width.


Archive | 1997

Semiconductor integrated circuit with protection circuit against electrostatic breakdown and layout design method therefor

Takashi Iida; Satoru Sumi; Hiroshi Shimizu; Akinori Tahara; Isao Amano; Tetsuya Nakajima


Archive | 1988

Semiconductor device with PN junction isolation for TTL or ECL circuits

Hiromu Enomoto; Yasushi Yasuda; Yoshiki Shimauchi; Akinori Tahara


Archive | 1987

Two-stage gate circuit providing inverted and non-inverted outputs

Hiromu Enomoto; Yasushi Yasuda; Akinori Tahara; Masao Kumagai


Archive | 1987

Logic circuit employing bipolar-transistors and stable upon starting-up of power supply therefor.

Hiromu Enomoto; Yasushi Yasuda; Masao Kumagai; Akinori Tahara


Archive | 1985

A GATE CIRCUIT FOR USE IN A MICROCOMPUTER SYSTEM

Hiromu Enomoto; Yasushi Yasuda; Akinori Tahara; Masao Kumagai


Archive | 1985

A logic circuit

Hiromu Enomoto; Yasushi Yasuda; Masao Kumagai; Akinori Tahara

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Tatsuya Yamazaki

Tokyo Institute of Technology

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Takashi Ito

Kansas State University

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