Yoshihiro Arimoto

Scaling theory for double-gate SOI MOSFET's

A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t/sub si/; gate oxide thickness t/sub ox/) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 mu m while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator. >

Novel high aspect ratio aluminum plug for logic/DRAM LSIs using polysilicon-aluminum substitute (PAS)

This paper describes a polysilicon-aluminum substitute (PAS) technique for single-crystalline aluminum plugs with aspect ratios of over 7 used for subquartermicron logic/DRAM LSIs. A via hole was filled with polysilicon by CVD, and aluminum was deposited on the planarized polysilicon plug. An aluminum plug was substituted for the polysilicon by annealing. We filled via holes having a minimum diameter of 0.175 /spl mu/m and a depth of 1.7 /spl mu/mn (an aspect ratio of about 10) with aluminum.

Boron Diffusion Through Pure Silicon Oxide and Oxynitride Used for Metal‐Oxide‐Semiconductor Devices

We studied boron diffusion in thin silicon oxides including pure SiO 2 and oxynitride that are used for metal-oxide-semiconductor transistors. We measured the boron penetration using secondary ion mass spectrometry. By comparing simulated and experimental results, we found that the boron diffusivity in pure SiO 2 , D PO , is 3.96 × 10 -2 exp (-3.65eVLkT) cm 2 /s, and that in oxynitride containing 4% nitrogen, D NO , is 3.42 × 10 -2 exp (-3.75 eV.kT) cm 2 /s

Simultaneous Temperature Measurement of Wafers in Chemical Mechanical Polishing of Silicon Dioxide Layer

The wafer temperature in chemical mechanical polishing (CMP) of silicon dioxide layers was measured. When the temperatures of both the polishing slurry and the polishing pad were controlled at 8° C, the measured wafer temperatures were 10-20° C. The temperature distribution affected the thickness of the polished oxide layer. When the wafer temperature was high, the oxide layer removal rate increased because of the increased reaction of the slurry with the oxide layer. It was clear that there was a linear relationship between the measured wafer temperature and the oxide layer removal rate. The effects of grooving several typical polishing pads for oxide layer polishing were investigated. It was found that grooves on the pad increased the uniformity of the removal of the oxide layer from the wafer.

Reconditioning-free polishing for interlayer-dielectric planarization

In chemical mechanical polishing (CMP) using a colloidal silica slurry with a pH of 10–11 for interlayer-dielectric (ILD) planarization, the removal rate of the oxide film drops off rapidly because the pad surface becomes flat during a CMP process. Thus we must recondition the polishing pad surface in order to obtain the rough polishing pad surface. In result, we can maintain a constant removal rate of the oxide film during the life time of the pad. We clarified that the alteration of the polishing pad surface was caused by the KOH solution in a conventional slurry. We also found that our newly developed MnO2 slurry could prevent the alteration of the polishing pad surface in reconditioning-free CMP.

Advanced Metal Oxide Semiconductor and Bipolar Devices on Bonded Silicon‐on‐Insulators

Silicon-on-insulator devices have problems with both performance and cost. We developed three advanced devices on bonded SOI produced using pulse-field-assisted bonding and selective polishing in an attempt to solve these problems. We tightly bonded highly implanted wafers, epitaxial wafers, and wafers covered with smoothed CVD oxide at temperatures below 1000 o C. We uniformly thinned bonded wafers by grinding, polishing, resistivity-sensitive etching, or selective polishing. We formed buried layers and buried electrodes by bonding and polishing techniques. Our high speed epitaxial-base transistor on 1-μm thick SOI has a cutoff frequency of 32 GHz

Thermal decomposition of native oxide on Si(100)

We investigated the thermal decomposition of native oxide on Si(100) under ultrahigh vacuum using high‐resolution x‐ray photoelectron spectroscopy (XPS). The native oxide was formed by wet chemical treatment (HCl/H2O2/H2O), a widely employed procedure for preparing atomically clean surfaces. XPS measurements revealed that high temperature heating (≳700 °C) leads to a remarkable alteration in Si 2p and O 1s spectra. After heating to 700 °C, the Si3+ structure increases and the O 1s full‐width‐at‐half‐maximum decreases. After heating to 800 °C, the Si4+ and O 1s intensity decreases but the Si2+ intensity remains almost unchanged. We suggest that the formation of volatile SiO is related to the Si3+ structure produced by high temperature annealing.

Thin-film quasi-SOI power MOSFET fabricated by reversed silicon wafer direct bonding

A quasi-SOI power MOSFET has been fabricated by reversed silicon wafer direct bonding. In this power MOSFET, the buried oxide under the channel and source regions is removed and the channel region is directly connected to the source body contact electrode to reduce the base resistance of the parasitic npn bipolar transistor. The quasi-SOI power MOSFET can suppress the parasitic bipolar action and shows lower specific on-resistance than that of the conventional SOI power MOSFET. The fabricated chip level quasi-SOI power MOSFET shows the specific on-resistance of 86 m/spl Omega//spl middot/mm/sup 2/ and on-state breakdown voltage of 30 V.

A New SOI-Lateral Bipolar Transistor for High-Speed Operation

We proposed a new SOI-lateral bipolar transistor. The device is featured by a thin base (simulated thickness was 80 nm) and base contact which was formed just on an intrinsic base. The device has sufficient junction breakdown voltage, but a current gain of 10, due to the degraded forward-biased emitter-base junction characteristic. The current gain was improved to 30 by keeping the base region about 2 µm from the highly arsenic-implanted emitter. The device structure seems to be ideal for a future high-speed bipolar transistor.

A new circuit simulation model of ferroelectric capacitors

A circuit simulation model of ferroelectric capacitors was developed. Because of the complicated voltage and time dependence of polarization switching, simulation of the hysteretic behavior was applicable in the limited condition where the voltage change was of a constant rate or step like. The new model consists of parallel element capacitors each of which has different coercive voltage, switching charge and switching response to the voltage change. The model can be implemented in a SPICE simulator with simple expression, and it successfully reproduces the voltage and time dependence of polarization change under arbitrary conditions. Circuit simulation using this model can easily predict the behavior of ferroelectric capacitors and problems in the device operation.