Akio Misaka

Determination of proximity effect parameters in electron‐beam lithography

A new empirical method for determining proximity parameters in electron‐beam lithography is introduced on the assumption that the proximity function is composed of two Gaussians. This method is based on the clearance of resist after development in the nonexposed square region surrounded by the latticed exposed one. Since there are many identical patterns arranged two dimensionally, statistically averaged data of proximity parameters is obtained without undertaking scanning electron microscopy for linewidth measurements. Theoretical considerations are combined with the experimental observations in order to calculate proximity parameters by the use of the design pattern.

Improved outline phase-shifting mask (OL-PSM) for reduction of the mask error enhancement factor

We propose a new resolution enhancement technology (RET) for enhancing the resolution of contact hole patterns. The technology uses an attenuated mask with phase shifting aperture. The phase shifter is laid out based on the OL-PSM and CL-PSM algorithm. These RETs are called “Mask Enhancer”. Aerial images of random hole patterns are strongly enhanced by using the Mask Enhancer. We used the Mask Enhancer in 100-nm hole pattern fabrication in ArF lithography. The process window is strongly improved and the MEEF is drastically reduced compared to att-PSM.

Optical proximity correction in DRAM cell using a new statistical methodology

An optical proximity correction algorithm based on statistical methodology is developed. The response surface function (RSF) for the CD in the lithographic process is extended by introducing variables for the mask pattern size. The values of process parameters and mask pattern size are concurrently optimized by using the RSF. This methodology allows design for manufacturability, considering error distributions of process parameters such as focus position and exposure dose. The algorithm is applied to a DRAM cell pattern. The result indicates the annular illumination with larger coherency than that of the conventional illumination improve the CD limited yield.

Application of alternating phase-shifting mask to 0.16 μm CMOS logic gate patterns

An application of alternating phase-shifting mask to 0.16 micrometers logic gate patterns is studied. A double exposure method using positive resist in KrF excimer laser lithography is applied to obtain random gate patterns. To optimize the exposure conditions, proximity effects for 0.16 micrometers line patterns under various combinations of NA and (sigma) are examined using an aerial image simulator. To control the linewidth in +/- 10% CD, mask bias according to the space width and the mask pattern with two adjacent apertures which transfers an isolated line are applied. By using these techniques, 0.16 micrometers logic gate patterns including SRAM are demonstrated.

Mask enhancer technology for 45-nm node contact hole fabrication

We have proposed a new resolution enhancement technology using attenuated mask with phase shifting aperture, named Mask Enhancer, for random-logic contact hole pattern printing. In this study, we apply a new mask blank on Mask Enhancer in order to prevent the light intensity loss caused by the mask topography effect. We also perform to expose the new Mask Enhancer on the first ArF immersion scanner, ASML AT1150i. We demonstrate that the new Mask Enhancer can achieve 45nm-node contact hole printing with sufficient lithographic performance with combination of immersion lithography.

Optical proximity correction considering process latitude

A two-step OPC approach, that consists of a cell level OPC and a chip level OPC, is proposed. The cell level OPC plays an important role on generating the layout design rules of gate patterns at the initial phase of technology development. The chip level OPC is dedicated to CD adjustment. The Cell level OPC includes the OPC patten generator and the verification part on the basis of a 3D aerial simulation. The effect of the OPC pattern is estimated, calculating the process windows. Cell layout patterns and OPC patterns are generated so as to maximize the process windows. The cell level OPC allows us to remove the error that breaks out in the cell size reduction process.

Hierarchical proximity effect correction for e-beam direct writing of 64-Mbit DRAM

A high-speed proximity effect correction system with two-level cell hierarchy processing has been developed to realize an accuracy-assuring electron beam (EB) direct-writing for high density VLSI. The system has two distinct advantages. First, a new hierarchial zoning algorithm is introduced to realize a data compaction for the total pattern transactions. Zone data or assemblies or patterns to be proximity-corrected are created by the zoning procedure. Frame region is associated with each zone in order to incorporate the effect of back-scattered electrons into the zone data. Second, a fast iterative technique is introduced for the proximity effect correction calculation based on a dos modulation method. A double Gaussian proximity function is used for describing the electron scattering. The present correction system was applied to 64 Mbit DRAM pattern with a 0.4 micrometers design rule. The total correction processing for the layer with maximum data volume was completed within four hours in CPU time. The patterns after delineation and development were successfully obtained by combining the present proximity effect correction with tri-layer resist process.

Mask enhancer technology with source mask optimization (SMO) for 2Xnm-node logic layout gate fabrication

Strong resolution enhancement technologies (RETs) combined with hyper-NA ArF immersion lithography with source and mask optimization (SMO) have become necessary to achieve sufficient resolution in 2Xnm node devices. Conventional SMO methods have focused on minimizing the edge placement error and/or the cost functions of dose, focus, and mask errors. This has not, however, resolved the conflict between line and gap patterns on logic gate layouts. One issue remaining in particular is the mask error enhancement factor (MEEF). Furthermore, the pattern shapes at the line end gaps of SRAM gates remain a major challenge for logic device manufacturers. To overcome these problems, we explain the importance of controlling the light intensity profiles at line end gaps, focusing on a Panasonic product called Mask Enhancer that comprises an attenuated mask with a phase shifting aperture and enables light intensity profiles to be controlled easily. We demonstrate the products effectiveness in printing gates with optimized illumination source shapes. A simulation experiment and a feasibility study confirmed that Mask Enhancer can improve the MEEF and pattern shapes at the line ends of SRAM gates.

Mask enhancer technology for sub-100nm pitch random logic layout contact hole fabrication

We have proposed a new resolution enhancement technology using attenuated mask with phase shifting aperture, named Mask Enhancer, for random-logic contact hole pattern printing. In this study, we apply Mask Enhancer on sub-100nm pitch contact hole printing with 1.35NA ArF immersion lithography tool, and ensure that Mask Enhancer can improve MEEF at resolution limit and DOF at semi-dense and isolated pitch region. We demonstrate printing a fine 100nm pitch line of contacts and isolated simultaneously with MEEF of less than 4 by using Mask Enhancer and prove that Mask Enhancer is one of the most effective solutions for random logic layout contact hole fabrication for 28nm node and below.

Mask enhancer technology on ArF immersion tool for 45nm-node CMOS with 0.249/spl mu/m/sup 2/ SRAM contact layer fabrication

We achieve the contact layer printing of 0.249/spl mu/m/sup 2/ SRAM by using mask enhancer (ME) technology and 0.85NA ArF immersion tool. In conclusion, we strongly propose that ME is one of the most effective solutions to perform 45nm-node contact printing with sufficient lithographic performance for 45nm-node LSI manufacturing.