Hiroyuki Umimoto

A 0.05 /spl mu/m-CMOS with ultra shallow source/drain junctions fabricated by 5 keV ion implantation and rapid thermal annealing

A 0.05 /spl mu/m-PMOSFET has been fabricated for the first time, together with a 0.05 /spl mu/m-NMOSFET. For this process, ultra shallow source/drain junctions were developed on the basis of 5 keV ion implantation technology and rapid thermal annealing. The short channel effect was suppressed and Gm max reaches 460 mS/mm for NMOS and 380 mS/mm for PMOS. The delay time per stage of unloaded CMOS inverter is 13.1 psec at the supply voltage of 1.5 V.<<ETX>>

SMART-P: rigorous three-dimensional process simulator on a supercomputer

A description is given of a three-dimensional process simulator, named SMART-P, that is based on the finite-difference approach to the supercomputer FACOM VP-100. To simulate the impurity redistribution and nonplanar structure in the Si/SiO/sub 2/ system, this simulator contains a three-dimensional oxidation model, an interaction model of impurities, a numerical model of interstitial-assisted oxidation-enhanced diffusion, and other process models. The numerical process modeling in the Si/SiO/sub 2/ system is described. The three-dimensional process modeling CAD (computer-aided design) has been realized by using efficient numerical algorithms based on the generalized coordinate transformation method. The capabilities of this simulator have been demonstrated in applications relating to both local oxidation of silicon (LOCOS) and trench-isolated 0.5 mu m MOSFET structures. >

Analysis of Dopant Diffusion and Defect Evolution during sub-millisecond Non-melt Laser Annealing based on an Atomistic Kinetic Monte Carlo Approach

n-type dopant diffusion during sub-millisecond (ms) non-melt laser annealing (NLA) is investigated through the experiments and atomistic KMC modeling. Laser-only annealing can improve the n-type dopant activation and achieve shallow junctions. KMC model with vacancy complexes indicates that laser-only annealing for nFET can achieve highly activated junctions and reduce dopant fluctuations in the channel region and that P is an attractive replacement for the As extension with laser-only anneal.Sub-millisecond (ms) non-melt laser annealing (NLA) is investigated through experiments and atomistic KMC modeling. NLA can improve the dopant activation dramatically and achieve shallow junctions. B diffusivity during sub-ms annealing is discussed for the first time. The KMC model with FnVm complexes indicates that the thermal budget of sub-ms annealing is too small for full defect evolution and one possible solution for defect stabilization is F co-implant

Three-dimensional numerical simulation of local oxidation of silicon

The nitride mask bending stress is modeled in three dimensions by using the beam bending theory. The stress effect on the oxide growth is taken into account for the accurate evaluation of the oxide shape. The three-dimensional behavior of oxide growth is investigated by using three typical mask structures, which are called the hole (contact), island, and line structures. The mask structure effect and narrow mask effect on the birds beak length are simulated and discussed in comparison with the experimental data obtained by the top-view scanning electron microscopy (SEM) observation. Three-dimensional effects of the oxide thickness of local oxidation of silicon (LOCOS) structures are predicted by comparing simulations with two-dimensional effects obtained by the cross-sectional SEM observation. It is found that the birds beak length at the corner of the mask edge is much enhanced in the hole structure and retarded in the island structure. This result is explained by the three-dimensional effect on the oxidant diffusion and the nitride bending stress. >

Numerical simulation of stress-dependent oxide growth at convex and concave corners of trench structures

A numerical simulation of oxide thinning at convex and concave corners of trench structures is discussed. The stress effect on the oxide growth is modeled by solving oxidation kinetic equations including stress-dependent physical parameters. The different mechanism for oxide thinning at both corners has been clearly revealed by a comparison of oxide shapes obtained by cross-sectional transmission electron microscope (TEM) photographs and simulations. The oxide thinning at convex corners is caused by the stress-dependent surface reaction, and the oxide thinning at concave corners is caused by the stress-dependent oxidant diffusion.<<ETX>>

Numerical modeling of nonplanar oxidation coupled with stress effects

The study focuses on the numerical solution method based on a finite-difference approach with the coordinate transformation method for simulating the nonplanar oxide growth. A relaxation technique is introduced to incorporate the stress effect into oxidation kinetic equations maintaining numerical stability. In addition, for simulating the stress-dependent oxide growth, the role of the boundary condition at the free-oxide surface is discussed. The present method allows an accurate evaluation of the local stress distribution in nonplanar oxide structures and realizes the precise simulation of oxide shapes under the large stress effect. They are demonstrated in applications to both the LOCOS process with thick nitride film and the trench oxidation process, which strongly depends on the oxidation-induced stress at trench corners. >

A self-aligned retrograde twin-well structure with buried p/sup +/-layer

A self-aligned retrograde twin-well structure with a buried p/sup +/-layer surrounding the n-well is presented. The retrograde twin well and buried p/sup +/-layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions, and the channel stop processes are eliminated by using tight spatial distributions of retrograde n- and p-wells. This simple process is compatible with both local oxidation of silicon (LOCOS) and trench isolation processes and allows a scalable CMOS structure for very tight n/sup +/-to-p/sup +/ spacing. The present CMOS structure provides high latchup immunity at 1.5- mu m n/sup +/-to-p/sup +/ spacing and good isolation characteristics without additional n- and p-channel stop dopings. >

A statistical critical dimension control at CMOS cell level

This paper reports a new statistical methodology for controlling the spreads of the CD (critical dimension) distribution in the lithography process. Response surface functions (RSF) for the CD in line and arbitrary gap patterns are introduced. The method allows sensitivity analysis of whole gate patterns at CMOS cell level.

SMART-II: a three-dimensional CAD model for submicrometer MOSFET's

The authors describe a three-dimensional CAD model for submicrometer MOSFETs. The model has been implemented in a three-dimensional process/device integrated simulator, SMART-II, using a supercomputer. The MOS device model for hot electron transport is based on a modified current relation including an electron temperature effect in an inhomogeneous field. The need for an improved mobility model in an inversion layer and an impact ionization model using the recent experimental data for the mean free path is discussed with emphasis on the numerical simulation for I/V characteristics of small-geometry MOSFETs from the threshold regime to the avalanche regime. It is found that this approach is effective in realizing a three-dimensional CAD model for 0.5- mu m MOSFETs. An application of the model reveals a three-dimensional effect of avalanche breakdown behavior in small-geometry MOSFETs. >

High speed 0.1 /spl mu/m dual gate CMOS with low energy phosphorus/boron implantation and cobalt salicide

A novel dual gate CMOS with low energy phosphorus/boron implantation and cobalt salicide is proposed. This technology suppresses boron penetration for pMOS, while maintaining high current drivability for nMOS with simple process steps. In addition, the drain junction capacitance of nMOS is drastically decreased, compared to a conventional MOSFET with arsenic source/drain. The delay time of CMOS ring oscillator was 28 ps, which is due to low junction capacitance and high current driving capability.