Kenji Kawakita

Proximity effect correction data processing system for electron beam lithography

A proximity effect correction system has been developed by utilizing an efficient dose modulation technique based on a double Gaussian proximity function. A shaped electron beam system is assumed to be used. Two improvements are made. First, an optimal exposure dose on each pattern is determined by a new fast iterative method. The optimal dose makes the development isocontour conform to the pattern specification fairly well. Second, a ‘‘simple cell unit algorithm’’ that one of identical cells is proximity‐corrected, and the result is used to the other remaining cells is introduced. This offers to both decrease the processing time and save the memory/disk space. The present system is applied to the data processing of scaled‐down version of an aluminum wiring layer pattern of 16 Mbit dynamic random access memory with its minimum dimension of 0.4 μm. The calculation is successfully completed within 1 h of CPU time on a 10 MIPS general‐purpose computer. The dimensional accuracy of 10% is confirmed experimenta...

A noncharging direct-write electron beam process for a trilayer resist by ion shower technology

Abstract In compensating the charging effect in electron beam direct writing on trilayer resists, we developed a new process of irradiating the bottom layer resist with a H+ ion shower. Thus the field butting error caused by the charging during electron beam exposure was eliminated. This process requires an extra ion shower irradiation step after the bottom layer coating in the conventional trilayer resist process. The sheet resistance of the bottom layer, 10 13 Ω/□ , was reduced to 10 8 Ω/□ at a dosage of 1 × 1016 H+ ions/cm 2. SIMS analysis showed that the relative carbon concentration of the bottom layer material increased at a higher H+ ion dosage. The reduction of the resistance was caused by the carbonating of the bottom layer resist. As a result, the charge from EB direct writing was easily dissipated through the bottom layer. By using this new trilayer resist process, the field butting error was decreased from 0.5 μm/3σ in a conventional trilayer resist process to less than 0.1 μm/3σ, which is equal to the error for the single-layer resist on the Si substrate. Thus 0.5 μm rule 16MdRAM patterns were successfully obtained by this new direct-writing EB resist process.

An E-Beam Direct Write Process for 16M-Bit DRAMs

For obtaining a very fine wafer pattern below half micron, direct write EB lithography has charging and proximity effect problems. A method of compensating for the charging problem is to use a 40 kV proton shower irradiation process which decreases the bottom layer resistance of the trilayer resist. The charge of the electron beam is dissipated through the bottom-layer resist. As for the proximity effect, we developed a proximity effect correction software system by dosage modification. The theoretical and experimental results showed that in a 2.2-micron-thick trilayer planarizing resist system, a 0.5-micron isolated line, 0.5-micron isolated space, and 0.5-micron contact holes were simultaneously resolved in a half-micron-thick top-layer resist. The resultant half-micron-rule 16M-bit DRAM patterns were successfully obtained on uneven topography of the processed wafer using EB direct write.

An E-Beam Direct Write Process For Half Micron DRAMS

Direct write electron beam (EB) lithography is expected to write a very fine wafer pattern below half micron for the development of the comming generation ULSIs. But direct write EB lithography has two main peculiar problems for obtaining such a very fine resist pattern on an uneven topography of a processed wafer. One is a pattern dimension deviation from the designed value due to resist topography and proximity effects. The other problem is pattern registration deviation due to charge-up in the EB-resist. In order to investigate the proximity effect. we evaluated the deposited energy density profile by a double gaussian Exposure Intensity Distribution ( EID ) function. The theoretical and experimental results showed that in a 2.2 micron thick trilayer planerizing resist system. both 0.5 micron isolated line and isolated space were simultaneously resolved in half micron thick top layer resist. To compensate the charge-up problem, we treated the bottom-layer by a brand-new ion shower material modification process. A 40 KV proton shower irradiation decreased the resistance of the bottom layer. The charge of the electron beam was dissipated through the bottom layer resist. The resultant half micron rule 16 M-bit DRAM patterns were compared with the optically exposed tri-level resist patterns. The optically exposed patterns also had an optical proximity effect and half micron patterns were not resolved even adopting the contrast enhancement lithographic ( CEL ) technology. On the other hand, we successfully obtained 16M-bit DRAM patterns on the uneven topography of the processed wafer using EB direct write.

High‐performance electron beam lithography for 0.5 μm semiconductor device fabrication

High‐performance electron beam (e‐beam) lithography is applied for fabricating contact holes with submicron size, using a new trilayer resist process. This technology consists of proximity effect correction software and the H+ ion shower irradiation technique onto a trilayer resist. The proximity effect correction software based on a dose modulation method was developed to control the dimensional accuracy of submicron patterns, by using the calculation of the double Gaussian exposure intensity distribution (EID) function. The dimensional accuracy of 0.5 μm contact hole and line and space patterns were kept within 0.05 μm. The H+ ion shower irradiation technique was adopted to decrease the charging problem. Ion shower was irradiated onto the bottom layer of the trilayer resist at 40 keV, 1×1016 ions/cm2. The sheet resistance of the bottom layer resist was decreased from 1013 Ω/⧠ to 107 Ω/⧠ by the H+ ion shower irradiation. The field butting error due to the charging problem was improved to 0.1 μm/3σ, and a...

0.1 µm Fine-Pattern Fabrication Using Variable-Shaped Electron Beam Lithography

It is shown that fine patterns with 0.1 µm feature size can be obtained based on a new method of multiple-shot exposure with a variable-shaped electron beam lithography system.

High Speed Bipolar ECL Devices Using a Vertically Isolated Self-Aligned Transistor

We have fabricated ECL devices such as ring oscillators and a 1/16 divider to evaluate the performance of a vertically isolated self-aligned transistor which is named VIST. This VIST has a birds beak-free oxide isolation and an inactive base of high impurity concentration formed extremely near the emitter region. Moreover, all the side walls of emitter, base and collector are covered with oxide film. Using VIST, propagation delay time of 160 psec was achieved in an ECL ring oscillator. The ECL divider operated at frequencies up to 2.5 GHz with 21 mW power dissipation per stage. This operating frequency is the highest value ever reported of silicon dividers.