Shinji Odanaka

Potential design and transport property of 0.1-/spl mu/m MOSFET with asymmetric channel profile

This paper describes potential design and transport property of a 0.1-/spl mu/m n-MOSFET with asymmetric channel profile, which is formed by the tilt-angle ion-implantation after gate electrode formation. The relation between device performance and transport property of the asymmetric 0.1-/spl mu/m device is explored by Monte Carlo simulations, and measured electrical characteristics. The self-consistent Monte Carlo device simulation coupled with a process simulator reveals higher electron velocity at the source end of the channel and velocity overshoot at the source side of the channel, and the smaller high-energy tail of the distribution in the drain. This transport property creates high drain current, large transconductance, and low substrate current of the 0.1-/spl mu/m n-MOSFET with asymmetric channel profile.

Narrow-width effects of shallow trench-isolated CMOS with n/sup +/-polysilicon gate

Narrow-width effects are discussed of n- and p-MOSFETs with shallow trench isolation. MOSFETs with n/sup +/-polysilicon gates were fabricated down to channel widths of 0.5 mu m by using a novel planarization process with an etch stop. The threshold behavior is characterized as a function of both the sidewall-implanted boron and the three dimensional process/device simulations. The trench-isolated n-MOSFET shows the narrow-width effect with excess boron doses implanted in the sidewalls. It is found that the lateral diffusion of sidewall-implanted boron induces enhancement of the edge current although the devices show narrow-width effects. The trench-isolated p-MOSFETs show narrow-width effects with the buried-channel mode and the inverse-narrow width effect when surface channel conditions dominate at threshold. It is found that the narrow-width effect of p-MOSFETs strongly depends on the threshold adjustment by means of counter doping. >

A practical trench isolation technology with a novel planarization process

We develop a new vertical-trench isolation method that utilizes a thin SiO2film in-between double photoresists for uniform top-resist coating and for an etch-back barrier, a poly-silicon film above active regions for an etch-back buffer and large tilt-angle boron ion implantations into the trench-sidewalls for narrow channel effect control. The Planarization with the Resist / Oxide / Resist and the Poly _Silicon (PRORPS) can isolate the whole surface of a 6 inch-diameter wafer very uniformly with a large process margin. The standard deviation of the threshold voltage of a n-channel MOS-FET (W/L= 10µm/0.8µm) over the whole wafer is 0.38 % at about 0.6 V threshold voltage. The narrow-channel-effect is controlled for FETs down to 0.5 µm channel width. The method is applied to the megabit SCC (Surrounded Capacitor Cell) DRAM developed here and the cells and the peripheral-circuits are isolated at the same time successfully.

A new isolation method with boron-implanted sidewalls for controlling narrow-width effect

A new isolation method for high packing density MOS devices has been developed. In this method the LOCOS technique is applied to wide isolation regions and the buried-oxide technique is applied to isolation regions less than 2 µm wide. No additional masks are needed in order to form SiO2film in the wide field regions because the photoresist is thicker near steps and inside the narrow trenches. For reducing the hump that appears in subthreshold current characteristics of n-channel MOSFETs, Using buried-oxide isolation, tilt-angle implantation to each of the four sidewalls is performed as a channel stop. The Sidewall channel stop can also control the narrow-channel effect.

A 0.05 /spl mu/m-CMOS with ultra shallow source/drain junctions fabricated by 5 keV ion implantation and rapid thermal annealing

A 0.05 /spl mu/m-PMOSFET has been fabricated for the first time, together with a 0.05 /spl mu/m-NMOSFET. For this process, ultra shallow source/drain junctions were developed on the basis of 5 keV ion implantation technology and rapid thermal annealing. The short channel effect was suppressed and Gm max reaches 460 mS/mm for NMOS and 380 mS/mm for PMOS. The delay time per stage of unloaded CMOS inverter is 13.1 psec at the supply voltage of 1.5 V.<<ETX>>

SMART-P: rigorous three-dimensional process simulator on a supercomputer

A description is given of a three-dimensional process simulator, named SMART-P, that is based on the finite-difference approach to the supercomputer FACOM VP-100. To simulate the impurity redistribution and nonplanar structure in the Si/SiO/sub 2/ system, this simulator contains a three-dimensional oxidation model, an interaction model of impurities, a numerical model of interstitial-assisted oxidation-enhanced diffusion, and other process models. The numerical process modeling in the Si/SiO/sub 2/ system is described. The three-dimensional process modeling CAD (computer-aided design) has been realized by using efficient numerical algorithms based on the generalized coordinate transformation method. The capabilities of this simulator have been demonstrated in applications relating to both local oxidation of silicon (LOCOS) and trench-isolated 0.5 mu m MOSFET structures. >

A high performance 0.1 /spl mu/m MOSFET with asymmetric channel profile

This paper describes nonequilibrium transport phenomenon, practical fabrication process, and potential design of an asymmetric 0.1 /spl mu/m n-MOSFET for the first time. The self-consistent Monte Carlo device simulation coupled with a process simulator reveals the carrier velocity overshoot at the source side of the channel. It is found that the 0.1 /spl mu/m MOSFET with asymmetric channel profile realizes high device performance due to the high carrier velocity.

Low voltage, low current, high speed program step split gate cell with ballistic direct injection for EEPROM/flash

By disassociating from the conventional planar Nch FET structure, a new step split channel device with a new mechanism of ballistic channel hot electron (CHE) injection promises viability in future EEPROM/flash applications. The new non-planar device exhibits fast program of /spl sim/100 ns, at a maximum internal voltage of 5 V and at low currents of less than 10 /spl mu/A.

A mobility model for submicrometer MOSFET simulations including hot-carrier-induced device degradation

The model presented includes the quantum effects of electrons in the inversion layer proposed by S.A. Schwarz and S.E. Russek (1983) and the surface scattering effects due to the interfacial charges. By comparison with experimental data from scaled MOSFETs, the limitation of K. Yamaguchis (1983) mobility model in submicrometer device simulations is implied, while the quantum channel broadening effects have been proven significant in turn. In addition, it is shown that the modeling of the screening effect of Coulomb scattering plays an important role in simulating the hot-carrier-induced MOSFET degradation. The model can predict the current-voltage characteristics within 5% accuracy for scaled MOSFETs down to 0.5- mu m, as well as the degradation of electrical characteristics due to hot-carrier effects for submicrometer MOSFETs. >

The dynamics of latchup turn-on behavior in scaled CMOS

This paper presents the dynamics of latchup turn-on behavior in scaled CMOS structures using an exact time-dependent and two-dimensional numerical analysis based on the finite-difference approach. Both the dynamics of surface-induced latchup triggering by a parasitic PMOSFET and direct forward biasing are examined to discuss the two-dimensional effects of parasitic devices in a scaled CMOS structure during latchup turn-on. In the case of an n-well scaled CMOS, the two-dimensional nature of the well structure plays an important role for surface-induced latchup.