Carmine Miccoli

Threshold-Voltage Instability Due to Damage Recovery in Nanoscale NAND Flash Memories

This paper presents a detailed investigation of the impact of cycling time and temperature on the threshold-voltage instability arising from damage recovery during data retention on nanoscale nand Flash. Statistical results from the programmed state show that instabilities result, on average, in a threshold-voltage loss, which increases logarithmically with the time elapsed since the end of cycling. The slope of the logarithmic behavior strongly depends on the electric field during data retention, the cycling dose, and the probability level at which the shift of the array cumulative distribution is monitored. Increasing the cycling time and temperature corresponds, instead, to an equivalent delay of the instant at which the first read operation on the array is performed. The delay is studied for a large variety of cycling and retention conditions, extracting the parameters required for a universal damage-recovery metric for nand.

Investigation of the threshold voltage instability after distributed cycling in nanoscale NAND Flash memory arrays

This paper presents a detailed experimental investigation of the cycling-induced threshold voltage instability of deca-nanometer NAND Flash arrays, focusing on its dependence on cycling time and temperature. When the array is brought to a programmed state after cycling, instability mainly shows up as a negative shift of its threshold voltage cumulative distribution, increasing with time and resulting from partial recovery of cell damage created in the previous cycling period. The threshold voltage loss displays a strong dependence not only on the tunnel oxide electric field during retention, but also on the cycling conditions. In particular, performing cycling over a longer time interval or at higher temperatures delays the threshold voltage transients on the logarithmic time axis. The delay factor is studied as a function of the cycling duration and temperature on 60 and 41 nm technologies, extracting the parameter values required for a universal damage-recovery metric for NAND.

Resolving discrete emission events: A new perspective for detrapping investigation in NAND Flash memories

We report the first experimental evidence of discrete threshold-voltage transients on high-density NAND Flash arrays during post-cycling data retention. Proper choice of experimental conditions eliminates the impact of averaging effects and disturbs on the transients, enabling clear detection of single charge emission events from/to the tunnel oxide of sub-30nm NAND Flash cells. A stochastic model for the discrete emission process was developed from experimental data, demonstrating that number fluctuation of charges trapped in the tunnel oxide and the statistical nature of their emission dynamics strongly affect the post-cycling data retention performance of the arrays. These results pave the way for further analyses of NAND Flash reliability, where the behavior of single electrons and defects can be monitored and facilitate detailed assessments of the fundamental scaling challenges arising from the discrete nature of charge trapping/detrapping.

Revisiting Charge Trapping/Detrapping in Flash Memories From a Discrete and Statistical Standpoint—Part II: On-Field Operation and Distributed-Cycling Effects

Starting from the theoretical background on the detrapping process in nanoscale Flash memories given in Part I of this paper [1], we address here the effect of idle periods, temperature, and program/erase cycles on the spectral distribution of detrapping events and, in turn, on threshold-voltage instabilities appearing during a data retention time stretch. In so doing, we come to a comprehensive model able to deal with threshold-voltage instabilities from whatever on-field usage or testing scheme of the memory array, carefully accounting for both charge trapping and detrapping, and reproducing distributed-cycling effects. The model represents a valuable tool for the predictive reliability analysis of Flash technologies and for the development of accelerated experimental schemes for the assessment of post-cycling thereshold-voltage instabilities coming from charge detrapping.

Assessment of distributed-cycling schemes on 45nm NOR flash memory arrays

This paper investigates the validity of distributed-cycling schemes on scaled Flash memory technologies. These schemes rely on the possibility to emulate on-field device operation by increasing the cycling temperature according to an Arrhenius law, but the assessment of the activation energy that has to be used on scaled technologies requires a careful control of the experimental tests, preventing spurious second-order effects to emerge. In particular, long gate-stresses required to gather the array threshold voltage (VT) map are shown to give rise to parasitic VT-drifts, which add to the VT-loss coming from damage recovery during post-cycling bake. When the superposition of the two phenomena is taken into account, the effectiveness of the conventional qualification schemes relying on a 1.1 eV activation energy is fully confirmed at the 45 nm NOR node.

Impact of Control-Gate and Floating-Gate Design on the Electron-Injection Spread of Decananometer nand Flash Memories

This letter investigates the impact of control-gate (CG) and floating-gate (FG) doping and geometry on the electron-injection spread (EIS) of nanoscale NAND Flash memories. Doping of CG polysilicon rules the reduction of the CG-to-FG capacitance when moving from the read to the program conditions, as a result of polysilicon depletion. The capacitance reduction is shown, however, to be nearly negligible for the EIS resulting from incremental step pulse programming, which, for the commonly adopted voltage steps, is mainly determined by the capacitance value in read conditions. Finally, the scaling trend of the CG-to-FG capacitance and of the EIS is addressed, discussing the evolution of the FG polysilicon in terms of geometry and dimensions.

A new spectral approach to modeling charge trapping/detrapping in NAND Flash memories

We present a semi-analytical model for the description of charge trapping and detrapping phenomena occurring during cycling and idle periods in NAND Flash memories. The model is based on a statistical distribution of detrapping time constants that is affected by the composition of cycles and idle periods and accounts for charge discreteness, statistical charge capture and emission and statistical distribution of the threshold-voltage shift due to single detrapping events. The model can reproduce the experimental data under different conditions and allows to develop and monitor accelerated schemes able to mimic realistic on-field usage of the memory device.

Cycling pattern and read/bake conditions dependence of random telegraph noise in decananometer NAND flash arrays

We conduct a thorough investigation of random telegraph noise (RTN) dependence on program/erase and read/bake conditions in state-of-the-art 1X and 2X Flash NAND technologies. We demonstrate that RTN depends only on the cycle number and not on the program level or cycling pattern. Moreover, if the cumulative distribution of RTN is considered, a negligible temperature dependence appears, in apparent contrast with thermal activation of single-trap time constants. RTN appears also to be independent of the read and bake temperature, although a slight asymmetry in the distribution tails is induced by charge detrapping. A Monte Carlo model is also presented to account for the experimental observations.

Time dependent threshold-voltage fluctuations in NAND flash memories: From basic physics to impact on array operation

Introduction: Random telegraph noise (RTN) during read and charge detrapping during data retention cause time dependent threshold voltage (VT) fluctuations in NAND flash memories [1-9]. This paper reviews and discusses the physics of these phenomena and the impact on NAND array reliability based on characteristics of aggressively scaled 2D planar NAND cells [10][11]. The discussion is further extended to 3D NAND.

String Current in Decananometer nand Flash Arrays: A Compact-Modeling Investigation

This paper presents a detailed compact-modeling investigation of the string current in decananometer nand Flash arrays. This investigation allows, first of all, to highlight the role of velocity saturation, low-field mobility, and drain-induced barrier lowering on the string current versus read voltage characteristics. Results are validated on a 41-nm technology for different positions of the selected cell along the nand string, different pass voltages, and different array background patterns. The effect of cycling on the string current is then investigated by means of postcycling bake experiments, showing that the impact of charge trapping/detrapping and interface state generation/annealing varies as a function of the read current level. Compact-modeling results display that, at low read currents, charge trapping/detrapping represents the main damage mechanism for the cells, while interface states come into play for read currents close to the string saturation level via mobility degradation.