Giovanni M. Paolucci

Resolving discrete emission events: A new perspective for detrapping investigation in NAND Flash memories

We report the first experimental evidence of discrete threshold-voltage transients on high-density NAND Flash arrays during post-cycling data retention. Proper choice of experimental conditions eliminates the impact of averaging effects and disturbs on the transients, enabling clear detection of single charge emission events from/to the tunnel oxide of sub-30nm NAND Flash cells. A stochastic model for the discrete emission process was developed from experimental data, demonstrating that number fluctuation of charges trapped in the tunnel oxide and the statistical nature of their emission dynamics strongly affect the post-cycling data retention performance of the arrays. These results pave the way for further analyses of NAND Flash reliability, where the behavior of single electrons and defects can be monitored and facilitate detailed assessments of the fundamental scaling challenges arising from the discrete nature of charge trapping/detrapping.

Revisiting Charge Trapping/Detrapping in Flash Memories From a Discrete and Statistical Standpoint—Part II: On-Field Operation and Distributed-Cycling Effects

Starting from the theoretical background on the detrapping process in nanoscale Flash memories given in Part I of this paper [1], we address here the effect of idle periods, temperature, and program/erase cycles on the spectral distribution of detrapping events and, in turn, on threshold-voltage instabilities appearing during a data retention time stretch. In so doing, we come to a comprehensive model able to deal with threshold-voltage instabilities from whatever on-field usage or testing scheme of the memory array, carefully accounting for both charge trapping and detrapping, and reproducing distributed-cycling effects. The model represents a valuable tool for the predictive reliability analysis of Flash technologies and for the development of accelerated experimental schemes for the assessment of post-cycling thereshold-voltage instabilities coming from charge detrapping.

Working Principles of a DRAM Cell Based on Gated-Thyristor Bistability

This letter discusses the working principles of a memory cell exploiting the bistability of a single nanoscale gated-thyristor to achieve high-performance DRAM operation (T-RAM cell). The device relies on the possibility to reach either of the two stable states of the thyristor by means of a fast low-to-high gate switch and depending on the amount of holes in the gated p-base. In particular, with proper selection of the low and high gate levels, the stationary hole concentration in the p-base leads the thyristor to its high current state while hole depletion results in an orders-of-magnitude lower anode current. This opens the possibility for a DRAM technology with a simple back-end process and fast WRITE and READ operations with low voltage requirements.

Fitting Cells Into a Narrow

This paper presents an in-depth comparative analysis of the major physical constraints to the width of the threshold-voltage distribution of a state-of-the-art NAND Flash array. The analysis addresses both time-0 placement by program-and-verify algorithms on fresh and cycled arrays and distribution widening during idle/bake periods. Results allow to identify how each physical effect impacts the threshold-voltage distribution as a function of array program conditions, temperature, cycling, and duration of idle/bake periods, providing clear hints for the design of next generation technology nodes.

V_{T}

This letter presents a detailed experimental investigation of the current-voltage characteristics of deca-nanometer gated-thyristors, highlighting that strong differences exist between the static and the dynamic operation of these devices. In particular, results reveal that the forward-breakover voltage determining thyristor turn-on does not depend only on the applied gate voltage, but also on the rise time of the applied gate pulse, decreasing for fast pulse fronts. This is explained in terms of a higher electron injection from the cathode to the anode triggering device turn-on when the gate switching time is shorter than that required for holes to leave the p-base.

Interval: Physical Constraints Along the Lifetime of an Extremely Scaled NAND Flash Memory Array

We present a semi-analytical model for the description of charge trapping and detrapping phenomena occurring during cycling and idle periods in NAND Flash memories. The model is based on a statistical distribution of detrapping time constants that is affected by the composition of cycles and idle periods and accounts for charge discreteness, statistical charge capture and emission and statistical distribution of the threshold-voltage shift due to single detrapping events. The model can reproduce the experimental data under different conditions and allows to develop and monitor accelerated schemes able to mimic realistic on-field usage of the memory device.

Dynamic Analysis of Current-Voltage Characteristics of Nanoscale Gated-Thyristors

We conduct a thorough investigation of random telegraph noise (RTN) dependence on program/erase and read/bake conditions in state-of-the-art 1X and 2X Flash NAND technologies. We demonstrate that RTN depends only on the cycle number and not on the program level or cycling pattern. Moreover, if the cumulative distribution of RTN is considered, a negligible temperature dependence appears, in apparent contrast with thermal activation of single-trap time constants. RTN appears also to be independent of the read and bake temperature, although a slight asymmetry in the distribution tails is induced by charge detrapping. A Monte Carlo model is also presented to account for the experimental observations.

A new spectral approach to modeling charge trapping/detrapping in NAND Flash memories

In this work, we present a reliability investigation of T-RAM cells, considering their read failure, data retention and endurance. Experimental results on decananometer devices reveal a successful cell operation solving the voltage trade-off for optimal performance on state-0 and state-1, whose origin is explained by clear pictures of the physical processes giving rise to read failure and limiting data retention. Moreover, endurance results appear very promising, with cell functionality preserved up to very high cycling doses.

Cycling pattern and read/bake conditions dependence of random telegraph noise in decananometer NAND flash arrays

This paper presents a detailed compact-modeling investigation of the string current in decananometer nand Flash arrays. This investigation allows, first of all, to highlight the role of velocity saturation, low-field mobility, and drain-induced barrier lowering on the string current versus read voltage characteristics. Results are validated on a 41-nm technology for different positions of the selected cell along the nand string, different pass voltages, and different array background patterns. The effect of cycling on the string current is then investigated by means of postcycling bake experiments, showing that the impact of charge trapping/detrapping and interface state generation/annealing varies as a function of the read current level. Compact-modeling results display that, at low read currents, charge trapping/detrapping represents the main damage mechanism for the cells, while interface states come into play for read currents close to the string saturation level via mobility degradation.

Reliability investigation of T-RAM cells for DRAM applications

By using our 16-nm NAND Flash technology as a test vehicle, in this paper, we summarize all the experimental evidence that we have gathered so far on the phenomenology of cycling-induced charge trapping/detrapping in Flash memories. In particular, results from experiments conceived to explore the dependence of charge detrapping on cell memory state reveal that the phenomenon involves more than the simple capture and emission of charge carriers in tunnel-oxide defects. Besides, the thermal activation of charge trapping is highlighted for the first time, along with the detailed dynamics leading to the increase of the trapped charge as cell cycling proceeds. These results allow to lay some cornerstones for the microscopic description of cyclinginduced charge trapping/detrapping in Flash memories. From these cornerstones, in the companion paper (Resnati et al., 2016), a new physical picture for the trapping/detrapping processes will be proposed and implemented in a statistical model able to reproduce their corresponding threshold-voltage instabilities over array lifetime.