Pranav Kalavade

A Program Disturb Model and Channel Leakage Current Study for Sub-20 nm nand Flash Cells

We have developed a program-disturb model to characterize the channel potential of the program-inhibited string during NAND flash cell programming. This model includes cell-to-cell capacitances from 3-D technology computer-aided design simulation and leakage currents associated with the boosted channel. We studied the program-disturb characteristics of sub-30-nm NAND cells using a delayed programming pulse method. The simulation results agree with the experimental data very well and show quantitative impacts of junction leakage current, band-to-band tunneling (BTBT) current, Fowler-Nordheim tunneling current, and channel capacitance on the program disturb. We further discuss the cell-scaling trend and identify that the BTBT current can be a dominant mechanism for the program disturb of sub-20-nm NAND cells.

Extreme Short-Channel Effect on RTS and Inverse Scaling Behavior: Source–Drain Implantation Effect in 25-nm nand Flash Memory

In 25-nm NAND Flash memory, source-drain implantation conditions significantly affect random telegraph signal (RTS). In this extremely short gate length regime, RTS is proportional to the effective gate length (Leff) which exhibits an “inverse scaling effect.” Process simulation reveals that the laterally straggled and diffused As atoms from source/drain are sufficient to change the effective boron concentration even in the center of the channel which changes macroscale potential profile for the short-channel effect but also changes RTS by modulating random discrete dopant (RDD) effect. This result continues up to 10 000 program/erase cycles which indicates that the defect generation rate for RTS is not changed under the relevant doping conditions. Modeling of the source-drain dopant distribution must include atomistic simulation for accurate prediction of the RDD effect in NAND Flash memory below 30 nm.

Highly Scalable Vertical Double Gate NOR Flash Memory

A Sub-50 nm body thickness (TSi), vertical channel (not FINFET), double gate, multi-bit NOR flash cell is fabricated on bulk-silicon substrate and is electrically characterized. This floating gate, conventional flash cell (no exotic materials), is potentially scalable with below 8F2 size beyond 32 nm node and is enabled by several key unit process innovations. The device is extensively characterized for program/erase, endurance, and charge interference on a shared thin body, which is important for scalability, density and multi-bit operation.

A Novel Spacer Process for Sub-10-nm-Thick Vertical MOS and Its Integration With Planar MOS Device

We demonstrate vertical capacitors using a novel spacer process capable of fin thickness down to 5 nm. We also integrate this process compatibly with planar devices on the same die using minimal additional mask steps. Various implant conditions, order of implant step, and starting substrate dopings are studied and best conditions identified through TSUPREM4 simulations and later through experiments to ensure process robustness and dopant tunability for the vertical devices as well as to ensure comparable performance for planar and vertical devices. In anticipation of usage of this process in a high-density environment, the impact of isolation density on the leakage characteristics of vertical capacitors is also studied. After simultaneously fabricating planar and vertical structures, electrical characterization using capacitance-voltage (C-V) and current-voltage (I-V) measurements is performed. Functional capacitors for both types of devices are obtained. Oxide thickness is backtracked using I-V, C-V, and TEM and yield consistent results. The leakage current shows expected trends with voltage and is successfully fitted using prevalent tunneling models. The vertical structures are found to suffer from two problems: a larger leakage current and an additional planar parasitic capacitance due to a finite polysilicon gate thickness. The larger leakage is attributed to thin corners as confirmed by higher leakage in structures having a larger fraction of corner area (higher isolation density structures). A modified novel vertical device process circumventing both these problems by yielding thicker bottom and corner oxides is proposed and experimentally demonstrated. Finally, a path to extending this process for vertical transistor fabrication is shown in simulations

Lateral gate-all-around (GAA) poly-Si transistors

High performance near-single grain poly-Si lateral gate-all-around (GAA) MOS transistors have been demonstrated. A high I/sub ON//I/sub OFF/ ratio of 10/sup 8/ and nearly ideal subthreshold slope of 67 mV/dec were achieved. These devices were fabricated using a novel technique for crystallization of a-Si. resulting in substantial improvements in transistor performance as well as uniformity without the use of self-implantation. or any external crystallization seeding agents. The technology is simple, scalable, and CMOS compatible and therefore attractive for 3-D device integration.

Ge in main-stream CMOS: a future or fancy?

Summary form only given. As scaling continues, attention is returning to germanium and Ge-on-insulator (GOI) MOSFETs. This paper considers whether Ge technology is a viable alternative or a fanciful diversion. It discusses the scalability of Ge MOSFETs, the use of high-k dielectrics, cost effectiveness, and the circuits most likely to benefit the most, such as low power, high performance, memory, and optoelectronics.