Akira Yamaoka

PACS: a parallel microprocessor array for scientific calculations

Pacs-32 is a prototype supercomputer used for a broad range of scientific calculations. It has a synchronizable MIMD processor array, and on the basis of this facility, it provides efficient nearest neighbor communication. Processors are combined into a rectangular array with endaround connections, and can synchronize at user-specified points with little overhead. The hardware has been constructed with 32 processors, and the operating software includes a high-level language. The Pacs-32 system has performed in a number of applications, such as Poisson equation solving, nuclear reactor calculation, aerodynamics, Monte Carlo simulation of plasma particles, and molecular dynamics modeling in solid state physics. The processor efficiency measure ranges from 78 percent through 99 percent in these applications. 12 references.

Hierarchical execution to speed up pipeline interlock in mainframe computers

This paper introduces a methodology, called hierarchical execution, which reduces stalls caused by pipeline interlocks such as data and control dependencies. Since a lot of software has been accumulated in mainframe computer systems as object code, it is important to improve performance without having to recompile the code for optimization. Our methodology consists of a simple pre-ALU that generates results, with shorter latency than the main ALU, asynchronously, which reduces the overhead especially for address generation interlocks and branch instructions. This method was implemented in Hitachis mainframe processors, M-680 and M-880. In M-680, the pre-ALU, together with the instruction decoder, processes instructions in superpipelined fashion, which further improves performance. The aggregate effect of hierarchical execution on CPU time, for evaluated benchmarks, is 10% on average, with only a 1.6% increase in hardware. Therefore, we can roughly say that the hierarchical execution method improved cost performance by 8%.