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IEEE Transactions on Computers | 1996

Hierarchical execution to speed up pipeline interlock in mainframe computers

Yooichi Shintani; Toru Shonai; Hiroshi Kurokawa; Kazunori Kuriyama; Akira Yamaoka

This paper introduces a methodology, called hierarchical execution, which reduces stalls caused by pipeline interlocks such as data and control dependencies. Since a lot of software has been accumulated in mainframe computer systems as object code, it is important to improve performance without having to recompile the code for optimization. Our methodology consists of a simple pre-ALU that generates results, with shorter latency than the main ALU, asynchronously, which reduces the overhead especially for address generation interlocks and branch instructions. This method was implemented in Hitachis mainframe processors, M-680 and M-880. In M-680, the pre-ALU, together with the instruction decoder, processes instructions in superpipelined fashion, which further improves performance. The aggregate effect of hierarchical execution on CPU time, for evaluated benchmarks, is 10% on average, with only a 1.6% increase in hardware. Therefore, we can roughly say that the hierarchical execution method improved cost performance by 8%.


Archive | 1987

Pipelined data processor capable of decoding and executing plural instructions in parallel

Kazunori Kuriyama; Yooichi Hitachi Tennoue Shataku B Shintani; Akira Yamaoka; Tohru Shonai; Eiki Kamada; Kiyoshi Inoue


Archive | 1987

Data processor for concurrent executing of instructions by plural execution units

Yooichi Shintani; Kazunori Kuriyama; Tohru Shonai; Eiki Kamada; Kiyoshi Inoue


Archive | 1987

Data processor for parallelly executing conflicting instructions

Eiki Kamada; Yooichi Shintani; Kazunori Kuriyama; Tohru Shonai; Kiyoshi Inoue


Archive | 1987

Pipelined parallel data processing apparatus for directly transferring operand data between preceding and succeeding instructions

Akira Yamaoka; Kenichi Wada; Kazunori Kuriyama; Yooichi Shintani


Archive | 1988

Information processor providing enhanced handling of address-conflicting instructions during pipeline processing

Kazunori Kuriyama; Yooichi Shintani; Tohru Shonai; Eiki Kamada; Kiyoshi Inoue


Archive | 1984

Coded decimal non-restoring divider

Akira Yamaoka; Kenichi Wada; Kazunori Kuriyama


Archive | 1994

Computers having cache memory

Hiroshi Kurokawa; Kazunori Kuriyama; Naohiko Irie


Archive | 1989

Instruction processor for processing branch instruction at high speed

Kazunori Kuriyama; Kenichi Wada; Akira Yamaoka


Archive | 1984

Decimal multiplier device and method therefor

Akira Yamaoka; Kenichi Wada; Kazunori Kuriyama

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