Kazunori Kuriyama
Hitachi
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Featured researches published by Kazunori Kuriyama.
IEEE Transactions on Computers | 1996
Yooichi Shintani; Toru Shonai; Hiroshi Kurokawa; Kazunori Kuriyama; Akira Yamaoka
This paper introduces a methodology, called hierarchical execution, which reduces stalls caused by pipeline interlocks such as data and control dependencies. Since a lot of software has been accumulated in mainframe computer systems as object code, it is important to improve performance without having to recompile the code for optimization. Our methodology consists of a simple pre-ALU that generates results, with shorter latency than the main ALU, asynchronously, which reduces the overhead especially for address generation interlocks and branch instructions. This method was implemented in Hitachis mainframe processors, M-680 and M-880. In M-680, the pre-ALU, together with the instruction decoder, processes instructions in superpipelined fashion, which further improves performance. The aggregate effect of hierarchical execution on CPU time, for evaluated benchmarks, is 10% on average, with only a 1.6% increase in hardware. Therefore, we can roughly say that the hierarchical execution method improved cost performance by 8%.
Archive | 1987
Kazunori Kuriyama; Yooichi Hitachi Tennoue Shataku B Shintani; Akira Yamaoka; Tohru Shonai; Eiki Kamada; Kiyoshi Inoue
Archive | 1987
Yooichi Shintani; Kazunori Kuriyama; Tohru Shonai; Eiki Kamada; Kiyoshi Inoue
Archive | 1987
Eiki Kamada; Yooichi Shintani; Kazunori Kuriyama; Tohru Shonai; Kiyoshi Inoue
Archive | 1987
Akira Yamaoka; Kenichi Wada; Kazunori Kuriyama; Yooichi Shintani
Archive | 1988
Kazunori Kuriyama; Yooichi Shintani; Tohru Shonai; Eiki Kamada; Kiyoshi Inoue
Archive | 1984
Akira Yamaoka; Kenichi Wada; Kazunori Kuriyama
Archive | 1994
Hiroshi Kurokawa; Kazunori Kuriyama; Naohiko Irie
Archive | 1989
Kazunori Kuriyama; Kenichi Wada; Akira Yamaoka
Archive | 1984
Akira Yamaoka; Kenichi Wada; Kazunori Kuriyama