Akito Yoshida

A study on package stacking process for package-on-package (PoP)

This paper outlines package stacking process guidelines for a package-on-package (PoP) configuration. PoP stacks currently in production or development consist of a bottom package containing a high performance logic device designed to receive a mating top package typically containing high capacity or combination memory devices. System manufactures achieve lowest cost and maximum logistical benefits, when these two components are sourced from different IC device suppliers then stacked in the final board assembly flow. Thus, the package stacking process is a key technology in order for system manufacturers to be able to select the top and bottom components from various suppliers. This is because each package may have a different warpage trend from room temperature to reflow temperature. In this study, Sharps chip scale package (top CSP) was mounted on Amkors bottom CSP to enable package stacking in order to know if packages from two suppliers can get a good solder joint after stacking. The top package is 152 balls CSP with 0.65mm pitch, and a 2-row format. The bottom CSP is 352 balls with 0.5mm pitch and a 4-row format. In both cases, the package size is 14mm times 14mm. Flux and solder paste provided by Senju metal industry were tested to stack the packages and mount them on test boards using a multifunctional placement machine manufactured by Panasonic factory solutions. While selecting the top package with minimum warpage, both at room and reflow temperature, we varied the warpage amount from 50 to 150 mum for the bottom package by changing the die size and then investigating the solder joint. The result showed that even in the case where the bottom package had large warpage, the solder joint of the top-to-bottom package was well formed by the fluxing process. However, we observed open solder joints between the bottom package and the test board when the conventional screen printing method was used. Prior to the board mounting, we applied the solder paste dipping process to the solder ball of the bottom package. This solder paste was newly developed to optimize rheology and powder size for package stacking. Using the solder paste dipping process, the solder joint yield was much improved even when the bottom package was warped. Using this solder paste dipping process for the top package, the same effect will be expected if the top package has a large warpage

High Density PoP (Package-on-Package) and Package Stacking Development

This paper presents information concerning high density package-on-package (PoP) development which utilizes 0.5 mm top land pitch with solder on pad (SOP). Depending on system configuration and end application PoP has inherent advantages over other packaging configurations (such as MCP or SCSP). The advantages offered by PoP in terms of memory flexibility and easy testing compared to ASIC+memory die stacking have been well documented in previous papers by Yoshida et al.. Thus, PoP has seen rapid adoption in consumer handheld electronics including the cellular and MP3 sectors to name a few. The demands of increased functionality coupled with footprint constraints naturally means that finer pitches need to be introduced into all packaging technologies. While this introduces its own set of challenges for traditional chip-scale-packages (CSPs) the situation becomes critical in the PoP structure since finer pitches translate into less standoff between the packages. It was for this reason that the investigation of SOP covered in this paper was deemed to be necessary. The paper covers a description of the test vehicle, commercial board assembly process and board assembly materials investigated. The resulting stacking yields and board level reliability (BLR) results are discussed in detail. These results show that package stacking yields are very much a factor of the materials selected for top package dipping as well as overall PoP package design. Overall stacking and BLR results conformed to high volume yield expectations.

Design and stacking of an extremely thin chip-scale package

This paper presents a study on package design and package stacking for the extremely thin Chip Scale Package (etCSP) that has a cavity at the center of the laminate package substrate and lead free solder halls. A 0.5mm thick CSP technology was developed and presented at the ECTC 2002. Package reliability level was proven to be robust by the cavity substrate structure. It passed MRT IEDEC Level 1, 1000 cycles of TIC (-55C/125C), 1000 hrs of T/H (85C/85%RH), IOOOhrs of HTS (150C), and 96hrs of HAST (130C/85%RH). However, because the package was face down format and the solder balls were located along the encapsulation area, the VO count was less than 200 with 12 mm body size. In order to develop a stackable, high VO count base package with a moderate VO count package mounted on top, we studied a face up design for the devices having more than 250 VOs. It was found that a 12 or 13 mm CSP could have around 300 VOs by adopting a face op format, and the total mount height was 1.2 mm after the 2 packages were stacked. In this presentation, the stackable package design and its reliability level are discussed.

Evaluation of raw substrate variation from different suppliers and processes and their impact on package warpage

Thin substrates have been used in more and more package-on-package (PoP) designs to meet the overall package thickness requirement. Low CTE cores are becoming more popular to reduce thin package warpage. On the other hand, substrates used in the same product are often sourced from multiple suppliers. Packages built with thin substrates sourced from different suppliers were found to have different end-of-line (EOL) package warpage. In this paper, 5 legs of substrates from 3 different suppliers were studied and compared with regard to raw substrate warpage, raw substrate modulus and CTE properties, and their reactions to 1× reflow thermal conditioning in order to understand any correlation to end-of-line package warpage. It was found that raw substrates sourced from different suppliers, or different processes in the same supplier, could have different levels of initial bare substrate warpage due to residual stress. Simulation results showed clear correlation between bare substrate warpage and EOL package warpage. However, such correlation was not observed with the limited measurement data collected. It was also found that properties (CTE and modulus) of finished composite substrates from different suppliers and processes could vary significantly, especially in the high temperature range. The difference in properties could be correlated to the difference at end-of-line package warpage in some cases. Further more, the substrates from different suppliers or processes could change their warpage, modulus and CTE properties in different ways after 1× reflow temperature conditioning. The study shows that it becomes more and more important to have better quality control of substrates sourced from different suppliers as substrate becomes thin and low CTE core is used.

A study on an Ultra Thin PoP using through mold via technology

This paper presents a study on an Ultra Thin PoP, Package on Package, using Through-Mold-Via Technology (TMV). The total height of the evaluated PoP is approximately 1.0 mm including both top and bottom packages. In recent years, package-on-package (PoP) has been rapidly adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. However, existing methods of making the PoP may not satisfy next generation applications that will require reduced memory interface pitches, higher memory interface pin-counts and reduced thickness. In this study, an existing 0.5mm pitch top package was utilized as a control. An Ultra Thin bottom PoP had to be developed to meet the 1.0mm stack height target which needs advanced thin material and process technologies. The stack height of 1.0mm requires higher warpage control challenge for the bottom package to support different die size applications. This Ultra Thin bottom PoP test vehicle was built in 12mm × 12mm body, 0.5mm top / bottom pitch, 0.15mm thick mold, and die sizes ranging from 5.0mmsq. to 8.7mmsq. This package was tested with 4-layer / 0.23mm thick and 2-layer / 0.17mm thick substrate. The total PoP height is expected to be approximately 1.0mm by SMT one pass reflow stacking of the top memory package on the bottom Ultra Thin logic package. The package warpage was compared for two package configurations. One is bare die structure with assumption of flip chip interconnect. The other is TMV, where the entire package is over molded, and through-mold vias are laser-drilled down to TMV pads for interface with a top memory package. Confirmation has been made that the TMV structure is capable of accommodating larger die compared to bare die structure. This is because CTE in the package can be controlled by both of the substrate and Epoxy Molding Compound (EMC). In addition, the TMV structure has a flatter and more stable warpage profile due to the over molded EMC structure and material properties selected. From the measurement result, warpage amount and direction greatly depend on substrate construction and die size. Based on warpage result, two test vehicle conditions were selected with TMV configuration to carry out Board Level Reliability (BLR) testing. The test vehicle was mounted on board with a typical package stacking process. After on-board reflow process, (i.e. top and bottom PoP packages were reflowed at one time), the yield for package stacking showed good results demonstrated even with the limited set up for this trial. The test vehicle passed Drop Test and TCT (Temperature Cycling Test) criteria.

Board level reliability study on three-dimensional thin stacked package

This paper discusses the optimal design for PS-etCSP to achieve reliable thermal fatigue life of solder joint. For this purpose design analysis was performed using both simulation and experimental approaches. Since reduction of warpage is most critical issue to ensure good solder joint connection for thin packages, parametric study was performed to find the optimal set of package outline dimensions using finite element method. Next to find the optimal design far solder joint reliability, 3D FEA fatigue model was established with non linear material properties of solder joint. Various factors such as ball land size, motherboard thickness and surface mounting type were studied. As a result, it is found that thin die with small size and small CTE molding compound is better for minimizing package warpage and larger opening size, thinner board and single mounting on board are good for solder joint reliability. The stack of package however has little effect on solder joint reliability. The effects of board thickness and surface mounting type (single/double) were investigated in terms of assembly stiffness and solder joint reliability. Simulation results showed good correspondence with experiment. The fatigue life and failure location predicted by simulation agreed well with experimental data. The fatigue life of optimal design was 1225 cycles for single PS-etCSP and 990 cycles for stacked PS-etCSP with single side mounting on board under the thermal cycling loading of temperature of -40/spl deg/C/spl sim/125/spl deg/C. Subsequently it can be concluded that optimal design of PS-etCSP can meet the requirement for most portable product applications.

An extremely thin BGA format chip-scale package and its board level reliability

This paper outlines a study of an extremely thin (0.50 mm overall profile height) CSP (etCSP) and its board level reliability. This BGA format CSP has lead free solder balls and has been developed to meet the demands of the products for the compact and light portable consumer market segment. The package contains a cavity in the center where the die is placed. Due to its low profile, the properties of the molding resin used affected the amount of warpage in this CSP. In order to keep the package as flat as possible, different mold cap resins were evaluated and two of them were compared in component and board level testing. Because of the package design and the fact that die bonding is not required the etCSP showed a very robust moisture resistance test (MRT) performance of Level 1 260/spl deg/C to JEDEC/IPC J-STD-020A Moisture Sensitivity Classification Testing. Board level reliability for the etCSP (176 I/Os) was examined and compared with that for a conventional laminate CSP (168 I/Os) with the same 12.00 mm sq. body size. It was found that the etCSP showed better results than the referenced CSP in some mechanical tests even though the ball pitch of the etCSP was 0.50 mm, while the reference package was 0.80 mm ball pitch.

Advanced Embedded Packaging for Power Devices

Power electronics has a great popularity in many industrial fields. Recently, in automotive industrial fields, the number of demand on electrical vehicles has been extremely rising. Those devices are required to have high thermal performance. However, conventional power device packages using wire are difficult to match that. So we have developed a new and expectable advanced package for power devices using embedded dies and RDL. We conformed that our package has a low electrical resistance and good thermal performance due to the heat dissipation through many via holes. To fabricate test vehicle, we designed process parameters around via structure particularly. We fixed aspect ratio concerning copper-filling plating, and DAF material for enough adhesion. And then we actually fabricated TV sample embedded TEG chip and live-die, and realized the via structure is completely filled and connected correctly by the simple I-V curve on this package. We are expecting this package to be promising for the future power devices with good thermal performance.

Fine pitch PoP introduction

Package-on-package (PoP) has been widely adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. Typical PoP solution is applied to logic processor as bottom package and memory device as top package. TMV® solution is being applied to reduce the warpage and achieve the fine pitch PoP and stable stacking performance. Currently, 0.4mm MIF(Memory Interface Pitch) is the minimum pitch under production and more fine MIF pitch is being requested because more functions are being integrated on chip then chip size becomes larger even wafer node is going narrower. To sustain the similar package size with larger chip size, fine pitch PoP is required. In this paper, 0.3 and 0.27mm MIF pitch PoP will be studied as a solution for fine pitch PoP and as a interface material between Top and Bottom package, solder ball and Cu post will be evaluated.