Akram Ditali

Building-in reliability: soft errors-a case study

A case is described for implementing building-in reliability. The case study deals with the phenomenon of soft-error rates in DRAMs. It is shown that the process begins with looking at output variables and then working backwards to identify the key input variables that affect the output variables. The authors demonstrate how monitoring the identified input variables leads to a stable process in manufacturing. In addition, they have identified a new source of alpha particles that contributes to the soft error rate of memory ICs, namely, the phosphoric acid used during wafer fabrication. The findings show that the raw materials used in wafer fabrication are at least as great a source of alpha particle emissivity as are packaging materials.<<ETX>>

Effects of wafer bow and warpage on the integrity of thin gate oxides

We have studied the effects of initial wafer bow and warpage on the integrity of thinner gate oxides grown by both furnace and rapid thermal processing (RTP) methods. There is evidence of a correlation between wafer warpage and bow to the charge‐to‐breakdown characteristics of the gate oxide. An almost linear increase in defect density was observed when plotted as a function of increasing wafer warpage. The lifetime (t50%) of the samples with initial warpage of 10 μm or less is reported higher than those with initial warpage of more than 60 μm for both furnace and RTP‐grown oxides. The value of bow for the warped samples was taken for cases with the highest positive and negative values so both kinds of shape trends could be investigated. With initial wafer warpage ranging from 4 to 70 μm, we present the results of wafer dimensional analysis and correlate these to defect density and lifetime studies for thin gate oxides.

Hot-carrier-induced degradation of gate dielectrics grown in nitrous oxide under accelerated aging

Gate oxides grown with partial and complete oxidation in N/sub 2/O were studied in terms of hot-carrier stressing. The DC lifetime for 10% degradation in g/sub m/ had a 15*improvement over control oxides not grown in a N/sub 2/O atmosphere. Further improvement in g/sub m/ degradation was observed in oxides that received partial oxidation as compared with control oxides. This improvement is due to the incorporation of nitrogen that reduces strained Si-O bonds at the Si/SiO/sub 2/ interface, leading to lower interface state generation (ISG). Improvements were also observed in I/sub g/-V/sub g/ characteristics, indicating a reduction of trap sites both at the Si/SiO/sub 2/ interface and in the bulk oxide. Improved gate-induced drain leakage (GIDL) characteristics as a function of hot-carrier stressing for partial N/sub 2/O oxides were observed over control oxides. However, severe drain leakage that masked GIDL was observed on pure N/sub 2/O oxides and is a subject for further study.<<ETX>>

Ultrathin oxide-nitride dielectrics for rugged stacked DRAM capacitors

Ultrathin dielectric materials that provide high capacitance values are needed for 64- and 256-Mb stacked DRAMs. It is shown that capacitance values as high as 12.3 fF/ mu m/sup 2/ can be obtained with ultrathin nitride-based layers deposited on rugged polysilicon storage electrodes. These films present the reliability and low leakage current levels required for 3.3-V applications. The nitride thickness, however, cannot be scaled much below 6 nm to avoid the oxidation-punchthrough mechanisms that appear when too-thin films are unable to withstand the reoxidation step.<<ETX>>

Uniqueness in activation energy and charge-to-breakdown of highly asymmetrical DRAM Al/sub 2/O/sub 3/ cell capacitors

Al/sub 2/O/sub 3/ cell capacitors for dynamic random access memory (DRAM) applications were tested using constant voltage, time-dependent dielectric breakdown (TDDB) tests. The capacitors had area-enhancing, hemispherical grain (HSG) polysilicon as bottom electrodes (BEs). These electrodes acted as points of high electric field, and eased charge injection into the Al/sub 2/O/sub 3/. As a result, the capacitors had highly asymmetric current-voltage (I-V) characteristics. Time-to-fails (TTFs) were polarity-dependent, and, thus, much worse for HSG injection. However, activation energy (E/sub a/) and charge-to-breakdown (QBD) obtained from conducting stress under opposite polarities were a unique function of the electric field only. The results point to a common, polarity-independent mechanism responsible for final breakdown, and the possibility that only the kinetics of degradation is electrode controlled. Good correlation with the thermochemical E model suggests that the breakdown mechanism in Al/sub 2/O/sub 3/ might be similar to SiO/sub 2/.

X-Ray Inspection-Induced Latent Damage in DRAM

For quality verification, an X-ray inspection process is commonly being used for evaluating obscured and defective solder joints in surface mount technologies such as BGAs and flip chips. Integrated circuits subjected to any form of radiation, ionizing or non-ionizing, may incur some amount of damage depending on the absorbed dose. Though most X-ray inspections for high-quality imaging require ionizing dose amounts that are considered inconsequential for device failure or non-functionality, the degree of latent damage must be carefully considered. This paper discusses X-ray induced vulnerabilities of high-density DRAM exposed to low ionizing radiation levels typical in X-ray inspection systems. We look at critical parameters and their sensitivity in relation to varying dose amounts of X-ray irradiation. In consideration of different methodologies of reducing radiation dose amounts and limiting device exposure, we propose a procedure for attenuating potentially harmful X-ray radiation levels while preserving quality images

Oxide‐nitride storage dielectrics on smooth and rough polycrystalline silicon layers

We demonstrate that for the same capacitance value, 9.5‐nm‐thick oxide‐nitride storage dielectrics deposited on rough polycrystalline silicon exhibit a lower leakage current and a higher lifetime than 5.9 nm layers on smooth polycrystalline silicon. Leakage current reduction of more than two orders of magnitude and a lifetime increase of more than three orders of magnitude are reported. These improvements are explained by the nitride bulk‐limited type of conduction. Our data show that textured storage capacitors have all the properties required for efficient fabrication of 64 megabit dynamic random access memories.

X-Ray Radiation Effect in DRAM Retention Time

For quality verification, an X-ray inspection process is commonly being used for evaluating obscured and defective solder joints in surface-mount technologies, such as ball grid arrays and flip chips. Integrated circuits subjected to any form of radiation, i.e., ionizing or nonionizing, may incur some amount of damage depending on the absorbed dose. Though most X-ray inspections for high-quality imaging require ionizing dose amounts that are considered inconsequential for device failure or non-functionality, the degree of latent damage must be carefully considered. This paper discusses X-ray-induced vulnerabilities of high-density dynamic random access memory exposed to low ionizing radiation levels typical in X-ray inspection systems. We look at critical parameters and their sensitivity in relation to varying dose amounts of X-ray irradiation. In consideration of different methodologies of reducing radiation dose amounts and limiting device exposure, we propose a procedure for attenuating potentially harmful X-ray radiation levels while preserving quality images.

Leakage current and reliability of thin nitride films on as‐deposited rugged polycrystalline silicon

The leakage current and reliability characteristics of thin oxide/nitride (ON) storage dielectrics on as‐deposited rugged polycrystalline silicon layers are discussed. Rugged capacitors showing capacitance improvements as high as 53% exhibit only a slight increase in leakage current when compared to smooth structures. Even though these capacitors have a shorter lifetime at high electric fields, time‐dependent dielectric breakdown data at various fields show that their field acceleration coefficient is larger. However, lifetime extrapolations to low operating fields might be inaccurate if the field enhancement at the electrode asperities is not taken into account for the rugged capacitors.

Correlating Wafer-Level TDDB Lifetime Projections to HTOL Gate-Oxide Failures

The power-law model provides a relatively good correlation between the wafer-level (WL) time-dependent dielectric breakdown (TDDB) test (highly accelerated) conducted on test structures and high-temperature operating life (HTOL) test (moderately accelerated) conducted on product. This is true when WL stress is configured identically to HTOL stress, and the difference in oxide area between the two devices under stress is taken into account for lifetime projections.