Viju K. Mathews

Highly reliable, high-C DRAM storage capacitors with CVD TA/sub 2/O/sub 5/ films on rugged polysilicon

The authors report on a highly reliable stacked storage capacitor with ultrahigh capacitance using rapid-thermal-annealed low-pressure chemical vapor deposited (LPCVD) Ta/sub 2/O/sub 5/ films ( approximately 100 AA) deposited on NH/sub 3/-nitrided rugged poly-Si electrodes. Capacitances as high as 20.4 fF/ mu /sup 2/ (corresponding to the thinnest t/sub ox.eff/ (16.9 AA) ever reported using LPCVD-Ta/sub 2/O/sub 5/ and poly-Si technologies) have been achieved with excellent leakage current and time-dependent dielectric breakdown (TDDB) characteristics. Extensive electrical characterization over a wide temperature range ( approximately 25-300 degrees C) shows that Ta/sub 2/O/sub 5/ films on rugged poly-Si electrodes have a better temperature stability in dielectric leakage and breakdown compared to the films on smooth poly-Si electrodes.<<ETX>>

Dishing effects in a chemical mechanical polishing planarization process for advanced trench isolation

We report the first detailed study of dishing effects in chemical mechanical polishing (CMP) of oxide films, observed during the development of an advanced CMP‐only trench isolation process. The degree of dishing has been determined for field widths ranging from 0.3 μm to 4 mm and was found to be highly pattern geometry (field width) sensitive, increasing from ∼0 nm at a field width of 5 μm and below to 200 nm at 4 mm. Although this dishing effect makes complete planarization in a large field oxide region (on the order of 1 mm) difficult, it poses no serious problem for trench isolation in narrow field regions due to its reduced effect at small field geometries.

Effects of post-deposition annealing on the electrical properties and reliability of ultrathin chemical vapor deposited Ta/sub 2/O/sub 5/ films

This paper reports the effects of post-deposition rapid thermal annealing on the electrical characteristics of chemical vapor deposited (CVD) Ta/sub 2/O/sub 5/ (/spl sim/10 nm) on NH/sub 3/-nitrided polycrystalline silicon (poly-Si) storage electrodes for stacked DRAM applications. Three different post-deposition annealing conditions are compared: a) 800/spl deg/C rapid thermal O/sub 2/ annealing (RTO) for 20 sec followed by rapid thermal N/sub 2/ annealing (RTA) for 40 sec, b) 800/spl deg/C RTO for 60 sec and c) 900/spl deg/C RTO for 60 see. Results show that an increase in RTO temperature and time decreases leakage current at the cost of capacitance. However, over-reoxidation induces thicker oxynitride formation at the Ta/sub 2/O/sub 5//poly-Si interface, resulting in the worst time-dependent dielectric breakdown (TDDB) characteristics.<<ETX>>

Trapping, conduction, and dielectric breakdown in Si/sub 3/N/sub 4/ films on as-deposition rugged polysilicon

Rugged polysilicon stacked capacitors recently emerged as the storage structures of choice for the manufacture of advanced DRAMs. The authors present the charge-trapping characteristics of such capacitors showing a capacitance increase of more than 50%. It is observed that electron trapping is dominant on rugged structures, whereas hole trapping is observed on smooth structures. Conduction and breakdown properties are also reported. Measurements show that rugged polysilicon capacitors provide the low leakage current, the sharp breakdown distributions, and the trapping characteristics needed for advanced DRAM applications.<<ETX>>

Hot-carrier-induced degradation of gate dielectrics grown in nitrous oxide under accelerated aging

Gate oxides grown with partial and complete oxidation in N/sub 2/O were studied in terms of hot-carrier stressing. The DC lifetime for 10% degradation in g/sub m/ had a 15*improvement over control oxides not grown in a N/sub 2/O atmosphere. Further improvement in g/sub m/ degradation was observed in oxides that received partial oxidation as compared with control oxides. This improvement is due to the incorporation of nitrogen that reduces strained Si-O bonds at the Si/SiO/sub 2/ interface, leading to lower interface state generation (ISG). Improvements were also observed in I/sub g/-V/sub g/ characteristics, indicating a reduction of trap sites both at the Si/SiO/sub 2/ interface and in the bulk oxide. Improved gate-induced drain leakage (GIDL) characteristics as a function of hot-carrier stressing for partial N/sub 2/O oxides were observed over control oxides. However, severe drain leakage that masked GIDL was observed on pure N/sub 2/O oxides and is a subject for further study.<<ETX>>

Highly reliable SiO/sub 2//Si/sub 3/N/sub 4/ stacked dielectric on rapid-thermal-nitrided rugged polysilicon for high-density DRAM's

Experimental results are presented demonstrating that by using rapid thermal nitridation (RTN) of rugged poly-Si surface prior to Si/sub 3/N/sub 4/ deposition, the quality and reliability of reoxidized Si/sub 3/N/sub 4/ dielectric (ON dielectric with an effective oxide thickness of about 35 AA) can be significantly improved over ON films on rugged poly-Si without RTN treatment. These improvements include significantly reduced defect-related dielectric breakdown, 10/sup 3/ * increase in TDDB lifetime, lower leakage current, and suppressed electron-hole trapping and capacitance loss during stress.<<ETX>>

Ultrathin oxide-nitride dielectrics for rugged stacked DRAM capacitors

Ultrathin dielectric materials that provide high capacitance values are needed for 64- and 256-Mb stacked DRAMs. It is shown that capacitance values as high as 12.3 fF/ mu m/sup 2/ can be obtained with ultrathin nitride-based layers deposited on rugged polysilicon storage electrodes. These films present the reliability and low leakage current levels required for 3.3-V applications. The nitride thickness, however, cannot be scaled much below 6 nm to avoid the oxidation-punchthrough mechanisms that appear when too-thin films are unable to withstand the reoxidation step.<<ETX>>

Ultra‐High Capacitance Nitride Films Utilizing Surface Passivation on Rugged Polysilicon

This paper describes high performance capacitors formed with silicon nitride dielectrics which meet the requirements for advanced stacked storage structures in 64 Mbit DRAM and beyond. A novel combination of a rugged polysilicon bottom electrode and an ultra-thin nitride deposited with a surface passivation technique was used. We show that these structures can achieve up to 12 fF/μm 2 for 3.3 V applications. We demonstrate that 4-nm thick nitride films which feature low leakage, high capacitance, and excellent reliability can be fabricated

Degradation of junction leakage in devices subjected to gate oxidation in nitrous oxide (MOS transistors)

Nitrided gate oxides offer several electrical and reliability advantages over conventional oxides and also provide a good barrier against impurity diffusion. Oxidation in nitrous oxide (N/sub 2/O) has been very successful in overcoming some of the problems associated with nitridation in ammonia. The authors have observed that the extent of N/sub 2/O oxidation has a strong detrimental effect on the drain leakage current of MOS transistors in the off state. This phenomenon has been identified to be caused by an increase in the active area junction leakage current.<<ETX>>

Oxide‐nitride storage dielectrics on smooth and rough polycrystalline silicon layers

We demonstrate that for the same capacitance value, 9.5‐nm‐thick oxide‐nitride storage dielectrics deposited on rough polycrystalline silicon exhibit a lower leakage current and a higher lifetime than 5.9 nm layers on smooth polycrystalline silicon. Leakage current reduction of more than two orders of magnitude and a lifetime increase of more than three orders of magnitude are reported. These improvements are explained by the nitride bulk‐limited type of conduction. Our data show that textured storage capacitors have all the properties required for efficient fabrication of 64 megabit dynamic random access memories.