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Dive into the research topics where Alan Hales is active.

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Featured researches published by Alan Hales.


international test conference | 1994

A serially addressable, flexible current monitor for test fixture based I/sub DDQ//I/sub SSQ/ testing

Alan Hales

The Quality Test Action Group (QTAG) was formed at the 1993 International Test Conference to define a standard for test fixture based off-chip quiescent current monitors for use in the production testing of CMOS integrated circuits. These quiescent current monitors will provide the I/sub DDQ//I/sub SSQ/ test instrumentation that is needed by the semiconductor industry. This paper proposes a standard serial interface to be used by ATE systems to communicate with the QTAG quiescent current monitors.


international conference on vlsi design | 2012

A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS

Raguram Damodaran; Timothy D. Anderson; Sanjive Agarwala; Rama Venkatasubramanian; Michael Gill; Dhileep Gopalakrishnan; Anthony M. Hill; Abhijeet Ashok Chachad; Dheera Balasubramanian; Naveen Bhoria; Jonathan (Son) Hung Tran; Duc Quang Bui; Mujibur Rahman; Shriram D. Moharil; Matthew D. Pierson; Steven Mullinnix; Hung Ong; David Thompson; Krishna Chaithanya Gurram; Oluleye Olorode; Nuruddin Mahmood; Jose Luis Flores; Arjun Rajagopal; Soujanya Narnur; Daniel Wu; Alan Hales; Kyle Peavy; Robert Sussman

The next-generation C66x DSP integrated fixed and floating-point DSP implemented in TSMC 40nm process is presented in this paper. The DSP core runs at 1.25GHz at 0.9V and has a standby power consumption of 800mW. The core transistor count is 21.5 million. The DSP core features 8-way VLIW floating point Data path and a two level memory system and delivers 40 GMACS or 10 GFLOPS floating point MAC performance at 1.25GHz.


international test conference | 2010

Towards effective and compression-friendly test of memory interface logic

V. R. Devanathan; Alan Hales; Sumant Kale; Dharmesh Kumar Sonkar

Cost and time-to-market considerations are strongly driving the need to improve the effectiveness of structural patterns for speed/voltage binning. In this paper we focus on improving the quality of testing memory interface paths for speed/voltage-binning. We propose DFT schemes that propagate faults through the memory that are effective with test compression. We also propose memory architectural enhancements to improve the effectiveness of ATPG patterns for Fmax identification. Both synchronous and asynchronous memories are targeted. Experimental results on an industrial ASIC core show the effectiveness of the proposed schemes with test compression. Initial silicon results from a 40-nm testchip is also presented and it proves that Fmax using the proposed scheme is very close to that of functional patterns, while Fmax using conventional schemes are more than 2X higher than that of functional patterns.


Archive | 2009

Enhanced control in scan tests of integrated circuits with partitioned scan chains

Alan Hales; Srujan Kumar Nakidi; Rubin A. Parekhji; Srivaths Ravi; Rajesh Tiwari


Archive | 2002

IC with comparator receiving expected and mask data from pads

Lee D. Whetsel; Alan Hales


Archive | 2006

Scan Sequenced Power-On Initialization

Lewis Nardini; Alan Hales


Archive | 2005

Identical core testing using dedicated compare and mask circuitry

Lee D. Whetsel; Alan Hales


Archive | 2003

On-chip reset circuitry and method

Alan Hales; Anthony M. Hill


Archive | 2010

Comparator receiving expected and mask data from circuit pads

Lee D. Whetsel; Alan Hales


Archive | 2013

Delay fault testing using distributed clock dividers

Ramakrishnan Venkatasubramanian; Alan Hales; William C. Wallace

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