Alan L. Roberts

A 2 ns zero wait state, 32 kB semi-associative L1 cache

A 32 kB, semi-associative bit dimension, L1 cache test site uses 0.5 /spl mu/m 2.5 V CMOS. The technology features an Leff of 0.25 /spl mu/m, a 7 nm Tox, shallow trench isolation, and a tungsten local interconnect. Four of the available five levels of metal are used. The cache consists of a data-storage array (DSA) macro, a content-addressable memory (CAM) macro, directory macro, and a memory built-in self-test (MBIST) state machine. Measured clock-to-DSA data-out access is 2 ns on nominal hardware. Access includes late-select generation from the CAM. The hardware cycles at access.

Use of print-simulations in accelerated yield learning for 22nm BEOL technology

Back-end-of-line (BEOL) patterning defects on logic circuits are challenging to find and often involve lengthy wafer processing times and costly failure analysis resources to detect. A print-simulation tool was developed to predict patterning fails of such circuits. Validity of the simulator was verified independently through hardware data. Layout constructs of a functional logic circuit were simulated and potential weak spots that were susceptible to patterning fail were identified. Patterning solutions were put in place to address these fails. Independent test-structures were designed to electrically test for pattern fidelity of some of these constructs early in the process flow to provide faster feedback. Test results from these test-structures indicated that any potential gross patterning issues have been resolved for the identified design constructs before mask order. Yield learning methodologies like this significantly shortened the cycle of learning of the 22nm BEOL process.