James J. Covino

A 2 ns zero wait state, 32 kB semi-associative L1 cache

A 32 kB, semi-associative bit dimension, L1 cache test site uses 0.5 /spl mu/m 2.5 V CMOS. The technology features an Leff of 0.25 /spl mu/m, a 7 nm Tox, shallow trench isolation, and a tungsten local interconnect. Four of the available five levels of metal are used. The cache consists of a data-storage array (DSA) macro, a content-addressable memory (CAM) macro, directory macro, and a memory built-in self-test (MBIST) state machine. Measured clock-to-DSA data-out access is 2 ns on nominal hardware. Access includes late-select generation from the CAM. The hardware cycles at access.