Reid A. Wistort

A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation

A Ternary Content Addressable Memory (TCAM) uses a two-phase search operation where early prediction on its pre-search results prematurely activates the subsequent main-search operation, which is later interrupted only if the final pre-search results contradict the early prediction. This early main-search activation improves performance by 30%, while the low-probability of a late-correct has a negligible impact on power consumption. This Early-Predict Late-Correct (EPLC) sensing with silicon-aware tuning enables a high-performance TCAM compiler implemented in 32 nm High-K Metal Gate SOI process to achieve 1 Gsearch/sec throughput on a 2048×640 bit TCAM instance while consuming only 0.76 W, resulting in an energy efficiency of 0.58-fJ/bit/search. Embedded Deep-Trench (DT) capacitance reduces power supply collapse by 53% while adding only 5% area overhead for a total TCAM area of 1.56 mm2 .

Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories

A memory sense-amplifier self-calibrates during sense-line precharge to reduce the required signal development and minimize data capture timing uncertainty caused by random device variation. When compared to conventional single-ended sensing, this method reduces sense time by 70% and decreases sense-power by 40%. The self-referenced sensing scheme (SRSS) is used to implement the search operation in content-addressable memory (CAM) testchip. Fabricated in 1V 65nm CMOS, this scheme achieves a 0.6ns search time on a 70bit sense-line while consuming only 0.99 fJ/bit/search. Measured search access time on a five bank 64times240bit ternary CAM including selective precharge is 2.2ns. Measured power consumption at 450MHz is 10mW. Hardware shows robust search operation over a voltage range of 0.6V to 1.7V

1Gsearch/sec Ternary Content Addressable Memory compiler with silicon-aware Early-Predict Late-Correct single-ended sensing

A Ternary Content Addressable Memory (TCAM) uses a two phase search operation where early prediction on its pre-search results prematurely activates the subsequent main-search operation, which is later interrupted only if the final pre-search results contradict the early prediction. This early main-search activation improves performance by 30%, while the low-probability of a late-correct has a negligible power impact. This Early Predict Late Correct (EPLC) sensing enables a high-performance TCAM compiler implemented in 32nm High-K Metal Gate SOI process to achieve 1Gsearch/sec throughput on a 2048×640bit TCAM instance while consuming only 0.76W. Embedded Deep-Trench (DT) capacitance for power supply noise mitigation adds 5% overhead for a total TCAM area of 1.56mm2.

A 0.9ns random cycle 36Mb network SRAM with 33mW standby power

This paper describes a 36Mb SRAM with an internal random cycle of 0.9ns and is capable of driving and receiving data at 1.1Gb/s/pin on input and output pins simultaneously. The 115mm/sup 2/ die is fabricated in a 0.13 /spl mu/m process. High-VT array devices are used to reduce array sub-threshold leakage by 22/spl times/. The SRAM features include an improved architecture that segments the 36Mb array into six equal 6Mb sextants. Each sextant supports 1/6th of the 36b I/O width. All sextants of the array are equally timed to reduce the fastest-to-slowest access skew from the previous architecture. Separate input and output pins provide concurrent read and write operations for two random addresses per cycle. The cycle-time is achieved using the improved architecture and a self-timed read to write (STRW) protocol. The STRW protocol improves cycle time by over 20%.

Improved Match-Line Test and Repair Methodology Including Power-Supply Noise Testing for Content-Addressable Memories

This paper describes a novel test and repair methodology for an embedded content-addressable memory (CAM) design. Exhaustive match-line testing is used to ensure correct search operation after manufacturing, while search margin testing is used to provide robust functionality for the life of the product. With CAM being one of the most power-hungry circuits on chip, it is also important to test the effects of CAM-induced power-supply noise. Programmable BIST patterns induce worst-case power-supply noise in the system and then test CAM sensitivity to it. Fails in the CAM are detected by BIST and repaired using row redundancy with word-line and match-line steering. Hardware results stress the importance of this test and repair methodology