Christopher S. Putnam

Ultralow-power SRAM technology

An ultralow-standby-power technology has been developed in both 0.18-µm and 0.13-µm lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage six-transistor (6T) SRAM cell sizes are 4.81 µm2 and 2.34 µm2, corresponding respectively to the 0.18-µm and 0.13-µm design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25°C and is less than 400 fA per cell at 1.5 V, 85°C. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the well-known gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.

ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-/spl mu/m CMOS technology

Historically, the failure mode of the nMOS/lateral n-p-n (L/sub npn/) bipolar junction transistor (BJT) due to electrostatic discharge (ESD) is source-to-drain filamentation, as the temperature exceeds the melting temperature of silicon. However, as the gate-oxide thickness shrinks, the ESD failure changes over to oxide breakdown. In this paper, transmission line pulse (TLP) testing is combined with measurements of various leakage currents and numerical simulations of the electric field to examine the failure mode of an advanced 0.1-/spl mu/m CMOS technology, which is shown to be through gate-oxide breakdown. It is also shown by I/sub D/-V/sub G/ and I/sub G/-V/sub G/ measurements that the application of nondestructive ESD pulses causes gradual degradation of the oxide well before failure is reached, under the (leakage current) failure criteria used. Finally, the latent effects of stress-induced oxide degradation on the failure current I/sub f/ of the nMOS/L/sub npn/ are studied, and it is shown that as the device ages from an oxide perspective, its ESD protection capabilities decrease.

Efficient and Accurate Schematic Transistor Model of FinFET Parasitic Elements

We present a schematic transistor model for multifinger multifin FETs, which greatly simplifies an initially complex network. The schematic finFET model accepts various finFET layout information and is accurate in predicting the overall finFET characteristics, including the effect of parasitic resistance (R) and capacitance (C) in a finFET.

Determining dominant breakdown mechanisms in InP HEMTs

We present a new technique for determining the dominant breakdown mechanism in InAlAs-InGaAs high-electron mobility transistors. By exploiting both the temperature dependence and the bias dependence of different physical mechanisms, we are able to discriminate impact ionization gate current from tunneling and thermionic field emission gate current in these devices. Our results suggest that the doping level of the supply layers plays a key role in determining the relative importance of these two effects.

Study of factors limiting ESD diode performance in 90nm CMOS technologies and beyond

The on-resistance and failure current of electrostatic discharge (ESD) protection diodes in 90 nm and 65 nm bulk CMOS technologies is determined largely by the resistance and failure of metal lines, contacts or vias. With design optimization, P/sup +//N-well ESD diodes fabricated in a 90 nm bulk CMOS technology achieved a forward voltage drop of 1.66 V at 2 A, an on-resistance of 0.27 /spl Omega/ and a 100 ns TLP failure current greater than 5 A with a junction capacitance of only 125 fF, area of 330 /spl mu/m/sup 2/ and anode perimeter of 300 /spl mu/m.

Characterization and investigation of the interaction between hot electron and electrostatic discharge stresses using NMOS devices in 0.13 /spl mu/m CMOS technology

In this paper, the high-current characteristics encountered during electrostatic discharge (ESD) events using NMOS/Lnpn protection devices in a 0.13 /spl mu/m CMOS technology are investigated for different device parameters. The effects of silicide blocking and hot electron (HE) shifts on the second breakdown current of the NMOS devices are studied. The impact of nondestructive ESD stressing on HE shifts is also studied for both silicided and nonsilicided devices.

NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13-/spl mu/m CMOS technology

In this paper, the high current characteristics encountered during electrostatic discharge (ESD) stress using nMOS/L/sub npn/ protection devices in a 0.13-/spl mu/m CMOS technology are investigated for different device parameters: channel length, channel width, gate-oxide thickness, and drain/source contact to gate (DCG/SCG) spacing. From leakage current measurements following ESD stress, it is concluded that the shorter (0.13 /spl mu/m) devices fail because of source/drain filamentation, whereas longer (0.3 /spl mu/m) devices with thin (22 /spl Aring/) oxide gate fail because of oxide breakdown. This conclusion is consistent with and supported by numerical simulations of the electric field. It is also supported by the observed effect of hot carrier stress on I/sub t2/. Hot carrier stress experiments additionally revealed that ESD stress can and does affect subsequent hot carrier degradation of the device.

Evaluation of ESD characteristics for 65 nm SOI technology

With aggressive scaling and continuous drive for higher performance requirements, electrostatic discharge is becoming a major reliability challenge for advanced integrated circuits. Products must be designed with proper ESD protection circuits to provide adequate robustness and as the limits of the device capability are reached, factors like device reliability due to ESD sensitivity became more critical. In this paper, the ESD characteristics of I/O elements in 65nm SOI technology are thoroughly evaluated. With an appropriate design implementation using these discrete elements, industry standard ESD robustness can be achieved.

Decoupling capacitor modeling and characterization for power supply noise in 3D systems

Decoupling capacitors are essential to reduce high transient current noise and to provide a low impedance power delivery path. 3D technology has several advantages for power delivery, and this work investigates the impacts of decoupling capacitors on through-silicon-via (TSV)-based 3D power networks using a novel hybrid modeling approach, i.e., combining electromagnetic (EM) and SPICE simulations. We first partitioned a 3D system into a number of components, extracted the RLGC parasitics for each decomposed physical element, and imported them into an assembled system-level equivalent circuit. Through comparing and analyzing the effectiveness of several decoupling strategies, design tradeoffs are made in selecting the proper values and placement of decoupling capacitors to ensure optimal power distribution solution in 3D architectures.

I/O Architecture For Improved ESD Protection In Deep Sub-Micron SOI Technologies

In this paper, the I/O structure described is based on a state of the art 65nm SOI technology designed for SRAM and logic applications (Leobandung et al, 2005). It is a twin-well partially depleted SOI (PDSOI) CMOS technology with gate oxide thicknesses of 1.05nm (SG) and 2.35nm (DG)