Lincoln Lai Kan Leung

A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-/spl mu/m CMOS process

A 1-V 24-GHz 17.5-mW fully integrated phase-locked loop employing a transformer-feedback voltage-controlled oscillator and a stacked divide-by-2 frequency divider for low voltage and low power is presented. Implemented in a 0.18-/spl mu/m CMOS process and operated at 24 GHz with a 1-V supply, the PLL measures in-band phase noise of -106.3 dBc at a frequency offset of 100 kHz and out-of-band phase noise of -119.1 dBc/Hz at a frequency offset of 10 MHz. The PLL dissipates 17.5 mW and occupies a core area of 0.55 mm/sup 2/.

A 1-V 9.7-mW CMOS Frequency Synthesizer for IEEE 802.11a Transceivers

A 1-V CMOS frequency synthesizer is proposed for wireless local area network 802.11a transceivers using a novel transformer-feedback voltage-controlled oscillator (VCO) for low voltage and a stacked frequency divider for low power. Implemented in a 0.18-mum CMOS process and operated at 1-V supply, the VCO measures a phase noise of -140.5 dBc at an offset of 20 MHz with a center frequency of 4.26 GHz and a power consumption of 5.17 mW. Its tuning range is as wide as 920 MHz (23%). By integrating the VCO into a frequency synthesizer, a phase noise of -140.1 dBc/Hz at an offset of 20 MHz is measured at a center frequency of 4.26 GHz. Its output frequency can be changed from 4.112 to 4.352 GHz by switching the 3-bit modulus of the programmable divider. The synthesizer consumes only 9.7 mW and occupies a chip area of 1.28 mm2.

Design of passive UHF RFID tag in 130nm CMOS technology

This paper presents a low-power, passive, UHF RFID tag design compatible with EPCTM C1G2 protocol. In order to reduce its cost, diode-connected NMOS in a standard CMOS technology is used instead of Schottky diodes. With the help of low-threshold-voltage, triple-well NMOS, a minimum input power of -7.6 dBm is achieved. A sub-1 V, low temperature-coefficient voltage reference using self-biased mutual compensation is proposed without large resistors to save the chip area. In addition, an energy-aware irregular clock structure, together with clock gating, achieves low power consumption in the baseband processor. The whole tag is implemented in a 130 nm CMOS technology and the total chip area is 1200 mum times 1220 mum.

A 1V Dual-Band VCO Using an Integrated Variable Inductor

An integrated variable inductor is proposed using an on-chip transformer to obtain 2 inherent resonant modes for band-switching applications. Employing such a variable inductor in a 0.18-mum CMOS process at a 1-V supply, a VCO is demonstrated to oscillate in 2 distinct frequency bands from 2.2 GHz to 3.6 GHz and from 10.7 GHz to 11.3 GHz. The VCO measures phase noise of around -135.5 dBc/Hz for the lower band and around -126.5dBc/Hz for the upper band at 10-MHz offset while consuming 5mW and occupying an area of 0.4times0.8 mm2

Low power injection locked oscillators for MICS standard

This paper presents two low power injection locked oscillators (ILOs): direct ILO and tail ILO, implemented in a standard 0.13-µm CMOS process. Both ILOs are based on current-reuse differential LC voltage controlled oscillator (VCO) with different injection locations: direct injection for direct ILO and current source injection for tail ILO. The current-reuse topology enables lower power dissipation of both ILOs. It is about 1.2mW (without output buffers) under supply voltage of 1.2-V. When the injected input signal power is 0dBm, direct ILO and tail ILO feature a wide locking range of 320MHz and 220MHz, respectively. The locking range covers the Medical Implantable Communications Service (MICS) band (402MHz–405MHz). Each of the proposed ILOs can be used as the driver stage of power amplifier in transmitter systems conforming to the MICS standard.

A 1-V, 9.7mW CMOS frequency synthesizer for WLAN 802.11a transceivers

A 1-V CMOS frequency synthesizer is proposed by using a transformer-feedback VCO for low voltage and a stacked divider for low power. Implemented in 0.18-/spl mu/m CMOS process, the synthesizer is operated with a 1 V supply while consuming 10mW and occupying an area of 1.28mm/sup 2/. It measures a phase noise of -139dBc/Hz at an offset of 20MHz with a center frequency of 4.256GHz. The frequency tuning range of the frequency synthesizer is measured from 4.114-4.352GHz with a total number of 16 channels.

Sub-mW

This paper presents a sub-mW, current-reused first-harmonic LC injection-locked oscillator (ILO) using in-phase dual-input injection technique. It can be used as a power oscillator in the injection-locked transmitter of wireless biomedical sensor nodes (WBSNs) integrated into a wireless body area network. A prototype chip, implemented in a standard 0.13-μm CMOS process occupying 200 × 380 μm, operates in the medical implantable communications service (MICS) band for medical implants. Measurement results show that the proposed ILO features a wide locking range of 800 MHz (150-950 MHz) at an input power of 0 dBm. More importantly, it has a high input sensitivity of -30 dBm to lock the 3-MHz bandwidth of the MICS band, while consuming only 660 μW at 1-V supply. This ultralow power consumption enables autonomous WBSNs.

LC

A 1V WLAN IEEE 802.11a CMOS transceiver integrates all building blocks on a single chip including a transformer-feedback VCO and a stacked divider for the synthesizer and 8-bit IQ ADCs and 8-bit IQ DACs. Fabricated in a 0.18-mum CMOS process and operated at a single 1-V supply, the receiver and the transmitter consume 85.7mW and 53.2mW, including the frequency synthesizer, respectively. The total chip area with pads is 12.5 mm2

Dual-Input Injection-Locked Oscillator for Autonomous WBSNs

A high-efficiency charge-pump regulator formed by the proposed reconfigurable charge pump is presented in this article. The voltage gain of the reconfigurable charge pump can be adaptively adjusted based on the input voltage and the regulated output voltage. Enhancement of power efficiency is therefore achieved by reducing the conduction loss of the cascaded linear regulator due to the optimised gain of the reconfigurable charge pump. The proposed charge-pump regulator was implemented in commercial complementary metal-oxide semiconductor (CMOS) 0.35 μm technology. The active chip area is 0.46 mm2. The input range is from 1.5 to 3.3 V. The experimental results show that the proposed charge-pump regulator improves the power efficiency by as much as 40% when regulated at 1.2 V.

A 1V Low-Power Single-Chip CMOS WLAN IEEE 802.11a Transceiver

This paper addresses design consideration and potential solutions for single-chip CMOS wideband RF transceivers. System architectures are discussed together with their challenges as compared to conventional narrow-band systems. At the circuit level, various wideband design techniques for wideband matching, wideband loading, and wideband frequency tuning range is explored. Finally, detailed design and measurement results of an UWB LNA, an UWB synthesizer, and a wideband VCO is presented.