Shuzuo Lou

A linearization technique for RF receiver front-end using second-order-intermodulation injection

A linearization technique is proposed in which low-frequency second-order-intermodulation (IM2) is generated and injected to suppress the third-order intermodulation (IM3). The proposed linearization technique is applied to both a low-noise amplifier (LNA) and a down-conversion mixer in an RF receiver front-end (RFE) working at 900 MHz. Fabricated in a 0.18 mum CMOS process and operated at 1.5 V supply with a total current of 13.1 mA, the RFE delivers 22 dB gain with 5.3 dB noise figure (NF). The linearization technique achieves around 20 dB IM3 suppression and improves the RFEs IIP3 from -10.4 dBm to 0.2 dBm without gain reduction and noise penalty while requiring only an extra current of 0.1 mA.

A Single-Chip UHF RFID Reader in 0.18

A single-chip UHF RFID reader that integrates all building blocks-including an RF transceiver, IQ data converters, and a digital baseband-is implemented in a 0.18 mum CMOS process. A high-linearity RX front-end and a low-phase-noise synthesizer are proposed to handle the large self-interferer, which is a key challenge in the reader RX design. Highly reconfigurable mixed-signal baseband architecture for channel-selection filtering is proposed to achieve power optimization for multi-protocol operation with different system dynamic ranges and data rates. The reader dissipates a maximum power of 276.4 mW when transmitting maximum output power of 10.4 dBm and receiving the tags response of -70 dBm in the presence of -5 dBm self-interferer while occupying 18.3 mm2.

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This paper presents the design and integration of a fully-integrated dual-conversion zero-IF2 CMOS transceiver for 9-band MB-OFDM UWB systems from 3.1 GHz to 8.0 GHz. The transceiver integrates all building blocks including a variable-gain wideband LNA, a single combined mixer for both RF down-conversion in RX and up-conversion in TX, a fast-settling frequency synthesizer, and IQ ADCs and DACs. Fabricated in a standard 0.18- mum CMOS process, the receiver measures maximum S11 of - 13 dB, maximum NF of 8.25 dB, in-band IIP3 of better than -13.7 dBm, and variable gain from 25.3 to 84.0 dB. IQ path gain and phase mismatches of the receiver chain are measured to be 0.8 dB and 4 deg, respectively. The transmitter achieves a minimum output P-1 dB of -8.2 dBm, sideband rejection of better than -42.2 dBc, and LO leakage of smaller than - 46.5 dBc.

CMOS Process

A 1-V WLAN IEEE 802.11a CMOS transceiver integrates all building blocks on a single chip including a transformer-feedback VCO and a stacked divider for the frequency synthesizer and 8-bit IQ ADCs and 8-bit IQ DACs. Fabricated in a 0.18-mum CMOS process and operated at a single 1-V supply, the receiver and the transmitter consume 85.7 mW and 53.2 mW, including the frequency synthesizer, respectively. The total chip area with pads is 12.5 mm2.

A 3.1 GHz–8.0 GHz Single-Chip Transceiver for MB-OFDM UWB in 0.18-

A 54 MHz-880 MHz low-noise variable-gain amplifier (LNA) for use in cable TV tuners is designed in a 0.18-mum CMOS process. An active shunt feedback is used to achieve wideband input matching without degrading the noise figure. Inductive shunt-peaking is employed at the output to extend bandwidth. The LNA gain can be tuned from 10 dB to 22 dB. The amplifier measures a NF of 2.8dB in the high-gain setting, IIP3 of 5.0dBm at low-gain setting and draws a current of 23mA from a 1.8-V supply

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This paper presents the design of a CMOS receiver front-end (RFE) with dual-conversion zero-IF architecture for multi-band OFDM (MB-OFDM) system covering the first 9 frequency bands from 3.1 GHz to 8.0 GHz, each with a bandwidth of 528 MHz. A 3-stage wideband variable-gain LNA and a novel mixer with bottom LO input devices are proposed. A fully integrated frequency synthesizer is included to generate the desired LO signals with a band switching time of less than Ins. Fabricated in TSMC 0.18mum CMOS process and operated at 1.5 V, the RFE measures a maximum noise figure of 8.1 dB and an in-band IIP3 of -11.1 dBm while consuming a total current of 81.5 mA

m CMOS Process

An ultra-wideband low-noise amplifier (LNA) is designed for software-defined radios (SDR). Noise-cancellation common-gate stage is combined with capacitive cross coupling for wideband input impedance matching and small noise figure (NF). T-coils and inductive peaking are employed to extend the output bandwidth and to reject the noise from the loading resistors. Linearization using second-order intermodulation injection is adopted to improve the IIP3. Operated at 1.5 V from 0.8 GHz to 10.6 GHz, the 0.13-mum CMOS LNA measures 16-dB gain, -12 dB S11, 3.4-5.6 dB NF, and 1.6-dBm IIP3.

A 1-V 86-mW-RX 53-mW-TX Single-Chip CMOS Transceiver for WLAN IEEE 802.11a

An 860MHz-960 MHz UHF RFID reader is designed in 0.18- μm CMOS that fully integrates an RF transceiver and a digital baseband. Highly reconfigurable mixed-signal baseband architecture for channel-selection filtering is proposed to achieve optimal power consumption for multi-protocol operation with different system dynamic ranges and data rates. In the talk mode with LNA bypassed, the RX measures a sensitivity of 70 dBm in the presence of a 5 dBm self-interferer. In the listen mode, LNA is turned on, and RX sensitivity is 90 dBm is measured. The TX achieves output power from -9 to lldBm with output P-ldB of 10.4 dBm.

A Wideband CMOS Variable-Gain Low-Noise Amplifier for Cable TV Tuners

A 1V WLAN IEEE 802.11a CMOS transceiver integrates all building blocks on a single chip including a transformer-feedback VCO and a stacked divider for the synthesizer and 8-bit IQ ADCs and 8-bit IQ DACs. Fabricated in a 0.18-mum CMOS process and operated at a single 1-V supply, the receiver and the transmitter consume 85.7mW and 53.2mW, including the frequency synthesizer, respectively. The total chip area with pads is 12.5 mm2

A 1.5-V CMOS Receiver Front-End for 9-Band MB-OFDM UWB System

This paper presents a complete CMOS dual-conversion zero-IF2 transceiver for 9-band MB-OFDM UWB systems from 3.1 to 8.0 GHz. The transceiver integrates all building blocks including a variable-gain wideband LNA, a single mixer for both RF down and up conversions in RX and TX, a fast-settling frequency synthesizer, and IQ ADCs and DACs. Fabricated in a standard 0.18-μm CMOS process, the receiver measures maximum Sll of -13dB, maximum NF of 8.25 dB, in-band IIP3 of better than -13.7 dBm, and variable gain from 25.3 to 84.0 dB. IQ path gain and phase mismatch of the receiver chain are measured to be 0.8 dB and 4deg respectively. The transmitter achieves a minimum output P-1dB of -8.2 dBm, sideband rejection of better than -42.2 dBc, and LO leakage of smaller than -46.5 dBc.