Albert Fazio

Future directions of non-volatile memory in compute applications

NANDs new position in the compute memory hierarchy imposes new considerations for scaling to smaller lithography nodes and tightly links NAND with the external controller. Likewise, widespread acceptance of future NVM in the compute memory hierarchy will be determined by ability to meet both cost and performance criteria.

A novel memory cell using flash array contactless EPROM (FACE) technology

A single transistor flash memory cell which utilizes channel hot electron injection for programming and Fowler-Nordheim tunneling for erase is described. This flash memory technology uses a buried N/sup +/ bitline to connect the memory transistors rather than metal and contacts. Elimination of contacts results in a 45% cell area shrink of the conventional ETOX cell (based on 1.0 mu m design rules). A 4.48 mu m/sup 2/ cell area is also realized by using a 0.8 mu m technology. In addition to this cell scalability, the diffusion corner induced erase threshold bimodality can be reduced due to the intrinsic stripe geometries in the memory array. Furthermore, this contact/metal related layout rules can be relaxed, which allows this contactless approach to be extended to future generations without requiring complicated contact processing. Hence, the flash array contactless EPROM (FACE) technology lends itself to a very compact cell as well as a more manufacturable process.<<ETX>>

A high density high performance 180 nm generation Etox/sup TM/ flash memory technology

A 180 nm-generation flash memory technology has been developed, optimized for small cell size, high performance low voltage operation and multi-level-cell and embedded logic capability. Memory cell scaling utilizes scaled trench isolation, self-aligned floating gates, cobalt salicided complementary poly gates, unlanded contacts and traditional dielectric and junction scaling. Low voltage performance is achieved with the inclusion of logic compatible NMOS and PMOS transistors, a triple well and 3 layers of metal interconnect. 16 Mbit flash memories with 0.38 /spl mu/m/sup 2/ cell size have been built on this technology as a yield and reliability test vehicle.

Reliability Comparison of Flotox and Textured-Polysilicon E2PROMs

The leading E2PROM technologies are FLOTOX and textured polysilicon. Both store data as charge on a floating gate, and both use electron tunneling to write this data, but the two use radically different tunnel oxides for this purpose. When tunneling is not involved, as in lifetest and data-retention tests, the two have similar reliability. This reliability can exceed that of SRAMs and DRAMs because the E2PROMs are less sensitive to low-voltage oxide breakdown and soft errors. When tunneling is involved, as in program/erase endurance, their reliability is radically different. FLOTOXs program window is well-controlled and stable, so that failure to write is rare; endurance is instead limited by defect-related tunnel-oxide breakdown leading to data loss. Textured poly has the reverse characteristics: the window closes, but breakdown is rare. This tradeoff affects scaling, since defect-related breakdown increases directly with memory size, whereas window closing does not. FLOTOX is therefore best suited for low densities, textured-poly for high densities. Endurance evaluations must account for the differences between the technologies.