Albert M. Chu

The daunting complexity of scaling to 7NM without EUV: pushing DTCO to the extreme

This paper reviews the most critical components of a ‘holistic’ DTCO flow for an advanced technology node and in doing so quantifies the differences between 7nm technology node definitions implemented with extreme ultraviolet and 193nm immersion lithography. The DTCO topics covered include: setting scaling targets for critical pitches, gear-ratios, and cell height; defining a set of patterning solutions, required RET restrictions, and resulting patterning cost; compiling physical design objectives to achieve power, performance, and area scaling; developing a set of standard cell logic cell architectures; and finally assessing achievable cell-level as well as macro-level scaling.

A one-million-circuit CMOS ASIC logic family

Metallization and device channel length enhancements to an existing 0.5-/spl mu/m CMOS process are exploited in the design of a high-density ASIC (application-specific integrated circuit) logic family. Wired circuit density exceeds one-million equivalent two-input NANDs, with typical gate delays of 250 ps at 3.3 V. A total of 17 different chip sizes are offered, along with several surface-mount package options. Both IBM and industry-standard design systems are supported, along with a cost effective LSSD-based test methodology.

A clock methodology for high-performance microprocessors

This paper discusses an effective clock methodology for the design of high-performance microprocessors. Key attributes include the clustering and balancing of clock loads, multiple clock domains, a balanced clock router with variable width wires to minimize skew, hierarchical clock wiring, automated verification, an interface to the Cadence Design Framework II™ environment, and a complete network model of the clock distribution, including loads. This clock methodology enabled creation of the entire clock network, including verification, in less than three days with approximately 180 ps of skew.

A Clock Methodology for High-Performance Microprocessors

This paper discusses an effective clock methodology for the design of high-performance microprocessors. Key attributes include the clustering and balancing of clock loads, multiple clock domains, a balanced clock router with variable width wires to minimize skew, hierarchical clock wiring, automated verification, an interface to the Cadence Design Framework II™ environment, and a complete network model of the clock distribution, including loads. This clock methodology enabled creation of the entire clock network, including verification, in less than three days with approximately 180 ps of skew.

A reduced circuit library design system

A reduced circuit library using triple-level metal CMOS consisting of nine primitive logic circuits and five latch kernels is proposed for a gate array library. A grouping program has been written to combine these circuits automatically into complex functions which are then hierarchically placed and wired to achieve the density and performance of a more complex library. This approach provides a set of complex functions which is optimized for each specific application while reducing the resource needed for library development and maintenance.<<ETX>>