Wagdi W. Abadeer

Structural dependence of dielectric breakdown in ultra-thin gate oxides and its relationship to soft breakdown modes and device failure

For the first time, we report strong channel-length dependence and weak channel-width dependence of soft breakdown modes and device failure for ultra-thin gate oxides. For channel lengths around 0.2 /spl mu/m, oxide-breakdown events in FETs cause a sharp increase in FETs off-current which permanently degrades the switching performance of short-channel devices; this is not observed for longer channel length FETs. The results also indicate that both hard- and soft-breakdown events have a common origin but manifest themselves differently depending on the test structure and geometry being measured.

Challenges for accurate reliability projections in the ultra-thin oxide regime

In this work, we discuss several important aspects of reliability projections, especially for ultra-thin oxides in a direct tunneling regime such as stress methodologies, the determination of projection parameters, and their dependence on stress conditions as well as their impact on reliability projection. Most importantly, we found that the Weibull shape factors and area dependence are key to understanding of the reliability limitations for ultra-thin oxides.

Ultralow-power SRAM technology

An ultralow-standby-power technology has been developed in both 0.18-µm and 0.13-µm lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage six-transistor (6T) SRAM cell sizes are 4.81 µm2 and 2.34 µm2, corresponding respectively to the 0.18-µm and 0.13-µm design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25°C and is less than 400 fA per cell at 1.5 V, 85°C. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the well-known gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.

Nonlinear characteristics of Weibull breakdown distributions and its impact on reliability projection for ultra-thin oxides

We report nonlinear characteristics of Weibull time-to-breakdown distributions and non-Poisson area scaling behavior observed on ultra thin oxides. We develop a numerical model to quantitatively account for these effects in the context of current modulation due to oxide thickness variations. It is found that without proper treatment of current modulation effect, the use of Weibull slopes at higher failure percentiles can lead to erroneous and pessimistic reliability projection.

Bias temperature reliability of n/sup +/ and p/sup +/ polysilicon gated NMOSFETs and PMOSFETs

A comparison of bias temperature reliability for submicron p/sup +/ and n/sup +/ polysilicon gated devices is presented. An instability associated with the p/sup +/ polysilicon gated devices that gives a negative Delta V/sub t/ and an interface-state buildup for positive bias temperature (+BT) was observed. This instability is explained in terms of the amount of the hydrogen-bonded component of moisture that remains in the gate electrode. It is further shown that a proper postmetallization anneal will significantly reduce this instability. Therefore, it is concluded that high BT reliability for p/sup +/ polysilicon gated devices can be achieved with process controls and actions that reduce the moisture in the device-active area. These controls provide an adequate reliability margin in dual work-function designs.<<ETX>>

Doping profile design for substrate hot carrier reliability in deep submicron field effect transistors

The authors explore the impact of substrate hot carrier emission on the design of submicron FETs. Performance requirements increase the vertical field for decreasing feature size in the deep submicron regime. This in turn significantly enhances the degradation sensitivity to substrate hot carriers. Models that support reliability data show the relationship between device stability, and the location of the peak channel doping concentration with respect to the Si-SiO/sub 2/ interface. It is well established that increased surface concentration alone has the effect of increasing the rate of substrate hot carrier emission due to higher surface fields. These results show that an optimum design tradeoff of the apparently conflicting requirements of device stability, off-current and performance can be achieved by proper choice of doping peak location when key process tolerances are accounted for.<<ETX>>

Key measurements of ultrathin gate dielectric reliability and in-line monitoring

High-performance CMOS products depend upon the reliability of ultrathin gate dielectrics. In this paper a methodology for measuring thin gate dielectric reliability is discussed in which the focus is upon the elements of those test structures used in the evaluation, the design of the reliability stress matrix, and the generation of engineering design models. Experimental results are presented which demonstrate the reliability of ultrathin gate dielectrics measured on a wide variety of test structures with dielectric thicknesses ranging from 7 to 3.5 nm. An overview is provided for thin gate oxide reliability that was measured on integrated functional chips-high-performance microprocessors and static random-access memory (SRAM) chips. The data from these measurements spanned the period from early process and device development to full production. Manufacturing in-line monitoring for thin gate dielectric yield and reliability is also discussed, with several case histories presented which show the effectiveness of monitors in detecting process-induced dielectric failures. Finally, causes of oxide fails are discussed, leading to the process actions necessary for controlling thin gate dielectric defects.

Investigation of Plasma Charging damage impact on device and gate dielectric reliability in 180nm SOI CMOS RF switch technology

The impact of charging damage from plasma processes on device and gate dielectric reliability is investigated for MOSFETs fabricated in an SOI CMOS RF Switch technology. Although results from voltage breakdown measurements do not reveal any indication of plasma damage, detrimental antenna effects are observed on the negative bias temperature instability (NBTI) and hot carrier device performance. With regard to NBTI in P-channel SOI MOSFETs in particular, relaxation experiments are carried out under various bias conditions. Recovery effects which are well known for intrinsic NBTI are also observed for the antenna devices, but are found to be reduced relative to that of control devices.

Long-term bias temperature reliability of P/sup +/ polysilicon gated FET devices

An instability was found to be associated with +BT stress for P/sup +/ poly-gated NMOSFETs (PNMOS) and PMOSFETs (PPMOS), but not with the N/sup +/ poly-gated devices (NNMOS and NPMOS). The instability with the P/sup +/ poly-gated devices, which is a decrease in threshold voltage (V/sub t/) and an increase in interface state density (D/sub it/), was significantly reduced following N/sub 2/ annealing at 400/spl deg/C. It is shown that adequate reliability for P/sup +/ poly-gated devices can be achieved for VLSI technologies. >

Behavior of SiO2 Under High Electric Field/Current Stress Conditions

Various results reported to-date by several investigators tend to give conflicting conclusions regarding the mechanism of dielectric degradation due to high electric fields. We have investigated the reasons for these differences and from this work have proposed a more unified model. We have found that as the electric field is increased first positive charges are created causing negative Vt shift. With higher E-fields a reversal in polarity of net charges was observed. Just prior to breakdown, the creation of electron traps was also accompanied by severe degradation in transconductance. This later degradation is due to interface damage giving rise to surface states. This degradation has the most detrimental effect on the dielectric life time. The effect of other levels of E-field/current injection stressing on life time is also investigated.