George M. Braceras

A 0.9ns random cycle 36Mb network SRAM with 33mW standby power

This paper describes a 36Mb SRAM with an internal random cycle of 0.9ns and is capable of driving and receiving data at 1.1Gb/s/pin on input and output pins simultaneously. The 115mm/sup 2/ die is fabricated in a 0.13 /spl mu/m process. High-VT array devices are used to reduce array sub-threshold leakage by 22/spl times/. The SRAM features include an improved architecture that segments the 36Mb array into six equal 6Mb sextants. Each sextant supports 1/6th of the 36b I/O width. All sextants of the array are equally timed to reduce the fastest-to-slowest access skew from the previous architecture. Separate input and output pins provide concurrent read and write operations for two random addresses per cycle. The cycle-time is achieved using the improved architecture and a self-timed read to write (STRW) protocol. The STRW protocol improves cycle time by over 20%.