Albert X. Widmer

A DC-balanced, partitioned-block, 8B/10B transmission code

This paperd escribes a byte-oriented binary transmission code and its implementation. This code is particularly well suited for high-speed local area networks and similar data links, where the information format consists of packets, variable in length, from about a dozen up to several hundred 8-bit bytes. The proposed transmission code translates each source byte into a constrained 10-bit binary sequence which hase excellent performance parameters near the theoretical limits for 8B/10B codes. The maximum run length is 5 and the maximum digital sum variation is 6. A single error in the encoded bits can, at most, generate an error burst of length 5 in the decoded domain. A very simple implementation of the code has been accomplished by partitioning the coder into 5B/6B and 3B/4B subordinate coders.

Single-chip 1062 Mbaud CMOS transceiver for serial data communication

This work implements the media independent functions specified in the emerging ANSI fibre channel standard at 1062.5 Mbaud. Integrated onto a single CMOS chip are: two phase-locked loops (PLL) for clock generation and clock recovery, a selectable 1B or 2B parallel interface with corresponding multiplexer and demultiplexer for parallel-to-serial and serial-to-parallel conversion, word alignment logic for byte synchronization, 8B/l0B coder and decoder, and high-speed differential CMOS PECL drivers and receivers for the serial I/O. The chip measures 3.9/spl times/4.5 mm/sup 2/ with 100 I/O and dissipates 1.2 W at 1062 Mbaud with a 3.6 V supply. This design achieves higher-speed operation than previous CMOS work with similar integration, and lower power dissipation with higher integration than bipolar implementations at comparable speeds.

Single chip 4/spl times/500 Mbaud CMOS transceiver

This CMOS chip replaces a 72-wire interface with 4 serial, duplex links, for relief of interconnect congestion in applications such as large switching systems. The design supports transmission at 1.6 Gb/s per direction in full-duplex mode and provides the user with a transparent interface. The data source provides fixed-length synchronous packets segmented into 4 parallel bytes along with parity and flag bits. The packet size can be programmed up to 4/spl times/64 B with a parameter loaded from an external controller. Data packets can he transmitted contiguously. During idle periods that are marked by a flag, the circuit generates and transmits fill packets, which start with a non-data Comma character. The Comma marks both byte and packet boundaries on a serial link. The Fill packets carry an idle sequence or diagnostic and control information such as Not Operational, Remote Wrap, or Unwrap. Each link carries 400 Mb/s, corresponding to 500 Mbaud after 8 B/10 B encoding.

CMOS circuits for Gb/s serial data communication

Introduction A key characteristic of ICs in many communication-related applications is the combination of analog circuits with digital logic, while maintaining maximum performance at minimum power and cost. This combination presents a number of challenges beyond basic circuit design issues, ranging from technology choice and simulation techniques to noise and crosstalk. This paper focuses on recent CMOS design work addressing these issues, with specific attention to the area of high-speed serial data communication. Serial baseband data links, whether using fiber-optic or coaxial cables, incorporate coders and decoders, highspeed multiplexors and demultiplexors, and low-speed clock synchronization, along with phase-locked loops for high-speed clock synthesis and recovery (Figure 1). In addition, specialized analog circuits are typically required to interface with the particular medium (e.g., a laser driver and optical receiver circuit if a fiber-optic cable is used). The requirements and circuits for these specialized functions can vary widely depending on the transmission medium; however, the building blocks shown in Figure 1 are common to almost all serial data links and are the focus of this paper. The basic function, while conceptually simple, presents a number of significant design challenges due to the wide range of clock speeds and the mixture of analog and digital circuits required. For example, the Fibre Channel standard [l] specifies a maximum data rate of 1063 Mbaud, or a bit interval of 940 ps for the serial data. Clock generation and recovery and data retiming must operate at this high data rate, with a timing resolution of a fraction of the bit interval. Typically, these functions are implemented using custom analog circuits in order to achieve the stringent timing requirements and high speed; however, relatively few transistors are required (-500). At the parallel end of the data chain, frame processing (address resolution, sequence generation, etc.) is done at a multiple-byte level, at clock speeds of 50 MHz or even slower. The timing requirements are modest by current standards, but moderate transistor counts (-5 X lo’) are required to implement this function.

Gb/s fiber optic link adapter chip set

A pair of chips containing all of the required high-speed analog and digital circuitry for a fiber-optic date link with byte-wide interfaces, has been designed, fabricated, and tested at 1 Gb/s using a 1- mu m E/D (enhancement/depletion) MESFET technology. The transmitter chip takes a byte-wide parallel data stream and converts it to a serial signal suitable for driving a laser diode. The receiver chip takes an optical input and provides a retimed parallel data output synchronized with byte boundaries. It is concluded that such chips will find applications in computer data communication where packaging density and cost are important issues.<<ETX>>

Single chip 4×500 Mbaud CMOS transceiver

A CMOS chip containing four 500-MBd serializer/deserializer pairs has been designed to relieve interconnect congestion in an ATM switch system. The 9.7 9.7 mm2 chip fabricated in a 0.8m technology is packaged on a ceramic ball grid array and dissipates 3.5 W. It replaces a 72-wire parallel interface with an eight-line serial interface transparent to the user and supports transmission at 1.6 Gb/s per direction in full-duplex mode. Virtually error-free operation in a system environment over electrical serial links having up to 9 dB loss at 500 MHz has been realized using signal predistortion for the serial bit stream and PLL clock recovery for each of the four receivers. Interface timing and serial-link driver strength are programmable.

A 50 to 400 Mbit/Sec Single Chip Fiber Optic Receiver Circuit

A high speed fiber optic receiver is described which uses a single chip to perform all of the electronic functions. These functions include low noise preamplification, amplification to a logic compatible signal level, and automatic level restoration which maintains the correct receiver decision point over a large range of optical input power. The receiver has operated at bit rates from 50 to 400 Mbit/sec with sensitivities as high as -33 dbm.