Dennis L. Rogers

Integrated optical receivers using MSM detectors

The performance of a metal-semiconductor-metal (MSM) detector when combined with preamplifier electronics is discussed, and it is noted that certain advantages due to its horizontal surface can result in receivers with fundamentally higher performance than that possible with vertical p-i-n detector designs. The sensitivity of optical receivers using a MSM detector is analyzed, and a set of scaling rules is used to compare a MSM receivers sensitivity with that of a similar receiver using a vertical p-i-n photodiode structure. Assuming identical preamplifier designs it is shown that the MSM-based receiver, except at very high bit rates, can in principle consistently outperform its p-i-n counterpart with as much as a 6-dB improvement in sensitivity. >

120-Gb/s VCSEL-based parallel-optical interconnect and custom 120-Gb/s testing station

A 120-Gb/s optical link (12 channels at 10 Gb/s/ch for both a transmitter and a receiver) has been demonstrated. The link operated at a bit-error rate of less than 10/sup -12/ with all channels operating and with a total fiber length of 316 m, which comprises 300 m of next-generation (OM-3) multimode fiber (MMF) plus 16 m of standard-grade MMF. This is the first time that a parallel link with this bandwidth at this per-channel rate has ever been demonstrated. For the transmitter, an SiGe laser driver was combined with a GaAs vertical-cavity surface-emitting laser (VCSEL) array. For the receiver, the signal from a GaAs photodiode array was amplified by a 12-channel SiGe receiver integrated circuit. Key to the demonstration were several custom testing tools, most notably a 12-channel pattern generator. The package is very similar to the commercial parallel modules that are available today, but the per-channel bit rate is three times higher than that for the commercial modules. The new modules demonstrate the possibility of extending the parallel-optical module technology that is available today into a distance-bandwidth product regime that is unattainable for copper cables.

A GaAs MESFET IC for optical multiprocessor networks

A GaAs, enhanced/depletion mode, self-aligned, refractory-gate, MESFET chip process and circuit family have been developed for the integration of fiber-optic data link functions (e.g. photodetection, amplification, clock recovery, and deserialization) on a single chip. These authors describe the process and present results on integrating a complete optical receiver, including the photodiode and clock recovery circuits, on one chip. The chip functions use over 2000 devices, and perform at 1-GB/s, while dissipating less than 300 mW of heat. This chip is the most complex high-performance optoelectronic integrated circuit reported to date. >

Monolithic integration of a 3-GHz detector/preamplifier using a refractory-gate, ion-implanted MESFET process

High-performance interdigitated metal-semiconductor-metal (IMSM) detectors and photoreceivers have been fabricated using a standard refractory-gate, ion-implanted MESFET process which was also used to fabricate complex digital circuits. A rise time of 110 ps has been observed for a detector-preamplifier combination implying a small-signal bandwidth of about 3 GHz. Detector responsivities as high as 0.45 A/W, and dark currents as low as 5 nA have been observed.

A high-speed, high-sensitivity silicon lateral trench photodetector

We report a novel silicon lateral trench photodetector that decouples the carrier transit distance from the light absorption depth, enabling both high speed and high responsivity. The photodetector, fabricated with fully VLSI compatible processes, exhibits a 6-dB bandwidth of 1.5 GHz at 3.0 V and an external quantum efficiency of 68% at 845 nm wavelength. A photoreceiver with a wire-bonded lateral trench detector and a BiCMOS transimpedance amplifier demonstrates excellent operation at 2.5 Gb/s data rate and 845 nm wavelength with only a 3.3 V bias.

High-speed 1.3 mu m GaInAs detectors fabricated on GaAs substrates

High-speed interdigitated metal-semiconductor-metal detectors have been fabricated on non-lattice-matched, semi-insulating, GaAs substrates using two GaInAs layers of differing indium concentrations to accommodate most of the lattice mismatch by interface misfit dislocations. Bandwidths as high as 3 GHz were measured with none of the detrimental low-frequency gain usually observed in this type of device. This is attributed to the inhibition of the surface trapping of photoinduced carriers by a graded pseudomorphic layer at the surface.<<ETX>>

Gb/s fiber optic link adapter chip set

A pair of chips containing all of the required high-speed analog and digital circuitry for a fiber-optic date link with byte-wide interfaces, has been designed, fabricated, and tested at 1 Gb/s using a 1- mu m E/D (enhancement/depletion) MESFET technology. The transmitter chip takes a byte-wide parallel data stream and converts it to a serial signal suitable for driving a laser diode. The receiver chip takes an optical input and provides a retimed parallel data output synchronized with byte boundaries. It is concluded that such chips will find applications in computer data communication where packaging density and cost are important issues.<<ETX>>

120 Gb/s VCSEL-based parallel optical link and custom 120 Gb/s testing station

A 120 Gb/s optical link (12 channels at 10 Gb/s/ch) has been demonstrated. The link operated at a BER of less than 10/sup -12/ with all channels operating and with a total fiber length of 316 m, which comprises 300 m of next generation (OM-3) multimode fiber (MMF) plus 16 m of standard grade MMF. This is the first time that a parallel link with this bandwidth at this per-channel rate has ever been demonstrated. For the transmitter, a SiGe laser driver was combined with a GaAs VCSEL array. For the receiver, the signal from a GaAs photodiode array was amplified by a 12 channel SiGe receiver IC. Key to the demonstration is the use of several custom testing tools, most notably a 12-channel pattern generator. The package is very similar to the commercial parallel modules that are available today, but the per-channel bit rate is three times higher than for the commercial modules. The new modules demonstrate the possibility of extending the parallel optical module technology that is available today into a distance/spl times/ bandwidth regime that is unattainable for copper cables.

High speed, lateral PIN photodiodes in silicon technologies

High speed, efficient photodetectors are difficult to fabricate in standard silicon fabrication processes due to the long absorption length of silicon. However, high performance servers will soon require dense optical interconnects with low cost and high reliability, and this trend favors monolithic silicon receivers over hybrid counterparts. Recently, lateral PIN photodiode structures have been demonstrated in silicon CMOS technology with little or no process modifications. Optical receivers based on these detectors have achieved record performance in terms of speed and sensitivity. This paper will discuss the advantages, issues and recent advances in silicon-based photodetectors and optical receivers. This includes the fastest photodetector ever implemented in a standard bulk CMOS process, a 13.9 Gb/s lateral trench detector implemented in a modified EDRAM process, and a >15 GHz pure germanium photodiode grown directly on a silicon substrate.

Multi Gbit/s, high-sensitivity all silicon 3.3 V optical receiver using PIN lateral trench photodetector

We report a 3.3 V silicon optical receiver consisting of a CMOS-compatible lateral trench PIN photodiode and a transimpedance amplifier that achieved a sensitivity of -17. 1 dBm at 2.5 Gb/s and demonstrated error-free (BER<10/sup -10/) operation up to 6.5 Gb/s at 845 nm. This is the highest reported sensitivity at data rates above 2.0 Gb/s and the fastest operation of any Si-based optical receiver.