Carl J. Anderson

The circuit and physical design of the POWER4 microprocessor

The IBM POWER4 processor is a 174-milliontransistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the design methodology, clock distribution, circuits, power, integration, and timing that enabled the design team to meet the project goals and to complete the design on schedule.

SOI for a 1-volt CMOS technology and application to a 512 Kb SRAM with 3.5 ns access time

In this paper a CMOS technology that is optimum for low voltage (in the I-volt range) applications is presented. Thin but undepleted SOI is used as the substrate, which gives low junction capacitance and no body effect. Furthermore floating body effects causes a reduction of subthreshold slope at high drain bias. This lowers the high-V/sub DS/ threshold to be used, which increases the current drive without significant increase in the off-current. This technology was applied to a high performance 512 Kb SRAM. Access time of 3.5 ns at 1 V was obtained.<<ETX>>

Circuit and technique for characterizing switching delay history effects in silicon-on-insulator logic gates

The delay of a partially depleted silicon-on-insulator complementary metal oxide semiconductor (MOS) logic gate can vary by 10% or more due to history effects. We describe and demonstrate a circuit and measurement technique with which one can measure history effects dominated by either the output rising (pMOS) or output falling (nMOS) characteristics of a multiple-input silicon-on-insulator gate. To precondition the floating-body voltages, any combination of inputs and number of switching events, arbitrarily configured with respect to timing and sequence, may precede an event to be measured.

Gb/s fiber optic link adapter chip set

A pair of chips containing all of the required high-speed analog and digital circuitry for a fiber-optic date link with byte-wide interfaces, has been designed, fabricated, and tested at 1 Gb/s using a 1- mu m E/D (enhancement/depletion) MESFET technology. The transmitter chip takes a byte-wide parallel data stream and converts it to a serial signal suitable for driving a laser diode. The receiver chip takes an optical input and provides a retimed parallel data output synchronized with byte boundaries. It is concluded that such chips will find applications in computer data communication where packaging density and cost are important issues.<<ETX>>

Josephson look-back analog to digital converter

A Josephson analog-to-digital (A/D) converter which uses a look-back algorithm to increase accuracy was designed and experimentally verified. The look-back A/D algorithm and its implementation in a Josephson 6-b A/D converter are described. High-speed measurements verified that the 3-b look-back A/D converter functions at 534 Msamples/s. The look-back algorithm increases the margins of an A/D converter that uses the lobes of a superconducting quantum interference devices (SQUIDs) threshold curve. The self-gating AND circuits (SGAs) give the A/D converter a short aperture time. The SGAs sample the analog signal in parallel and then the look-back logic decodes the twos complement outputs in series with only one stage of logic per bit. With a stable process the look-back A/D converter can be generated on chip.<<ETX>>

Thermal noise in digital Josephson devices

A method of accurately estimating the I/sub 0/ (critical current) of a Josephson junction (JJ) with thermal noise was developed by measuring the effective thermal noise temperature of a JJ. The effective thermal noise temperature of various JJ devices was measured and calculated. The JJ devices evaluated included inductively and resistively coupled logic devices and JJ devices in the presence of various noise sources. The noise sources included room-temperature resistors, switched JJ devices, and JJ devices in the linear I-V region beyond the gap. The R/sub NN/ compensator is shown to result in a noise temperature of about 6 K at an interferometer. The addition of a shunt junction lessens the noise penalty introduced by the compensator. A switched isolation interferometer in a two-input AND gate contributes negligible noise at the injection device. It is also shown that bandwidth connections to room-temperature equipment result in very large excess noise and require special input and output circuits on the chip.<<ETX>>

Beyond innovation: dealing with the risks and complexity of processor design in 22nm

This talk will describe the challenges of high-performance microprocessor designs in 22nm and beyond. The focus of the talk will be on addressing the risks and complexity of this very demanding design domain and what lies beyond the innovation that has been the driving engine of technology so far.

One look into the future of CMOS chip design

Both the physics and financial challenges of CMOS scaling to 22nm and beyond will be discussed. The effects of the possible slowing of future CMOS technology generations on CMOS chip design and methodology will be hypothesized.

Beyond innovation: Dealing with the risks and complexity of processor design in 22nm

Current and future Si technologies allow microprocessor designs to contain billions of transistors. Design tool and methodology improvements have allowed designers to implement microprocessors that have exponentially grown to billions of transistors with design teams that have only modest growth in size. Innovations have allowed technology feature sizes to scale to almost tenth of the wave length of light used to define them. This has added significant complexity to the technology and designs. This paper discusses the importance of discipline and risk management in the design of new high performance microprocessors in advanced technologies. Innovation is very important in these designs but the design costs have to be assessed and the risks managed.

Josephson compensating junction logic

A Josephson superconducting quantum interference device (SQUID) digital logic family was developed that uses the R/sub nn/ region of a Josephson junction (JJ) to compensate for variations in where R/sub nn/ is the effective resistance of a JJ in the linear I-V region beyond the gap. The basic compensating junction logic (CJL) circuit is two 2-input-OR 1-2-1 interferometer isolators that, when switched, inject current into a 2-input-AND 1-2-1 interferometer. The R/sub nn/ region of several JJs is used in series with a resistor to set the current from the power supply to the 2-input-OR interferometers. The 2-input-AND interferometer is implemented with both current injection and magnetic coupling. The latch circuit uses both current injection and magnetic coupling design techniques to increase the range of I/sub O/, inductance, and resistance variation over which the latch will function correctly. Experimental measurements of CJL circuits are described.<<ETX>>