John F. Ewen

Single-chip 1062 Mbaud CMOS transceiver for serial data communication

This work implements the media independent functions specified in the emerging ANSI fibre channel standard at 1062.5 Mbaud. Integrated onto a single CMOS chip are: two phase-locked loops (PLL) for clock generation and clock recovery, a selectable 1B or 2B parallel interface with corresponding multiplexer and demultiplexer for parallel-to-serial and serial-to-parallel conversion, word alignment logic for byte synchronization, 8B/l0B coder and decoder, and high-speed differential CMOS PECL drivers and receivers for the serial I/O. The chip measures 3.9/spl times/4.5 mm/sup 2/ with 100 I/O and dissipates 1.2 W at 1062 Mbaud with a 3.6 V supply. This design achieves higher-speed operation than previous CMOS work with similar integration, and lower power dissipation with higher integration than bipolar implementations at comparable speeds.

A 2.4-GHz silicon bipolar oscillator with integrated resonator

A 2.4 GHz fully-monolithic silicon-bipolar oscillator circuit implemented in a 12 GHz BiCMOS technology is presented. The integrated resonator circuit uses three different versions of a 2 nH multilevel inductor and a wideband capacitive transformer. The measured Q factor is 9.3 for the three-level inductor. An oscillator phase noise of -78 dBc/Hz is achieved at 20 kHz offset. The circuit dissipates 50 mW from a 3.6 V supply.

GaAs fiber-optic modules for optical data processing networks

A high-speed, highly integrated fiber-optic data communications link is described. It consists of a transmitter module containing a GaAs integrated circuit and a laser array with fiber array pigtail, and a receiver module containing a GaAs OEIC with a fiber array pigtail. The performance of the link at 1 Gb/s is presented with emphasis on the crosstalk and noise issues with those high levels of integration. Measured error rates as low as 10/sup -15/ confirm that these highly integrated link adapters are suitable for use in data processing networks. >

CMOS circuits for Gb/s serial data communication

Introduction A key characteristic of ICs in many communication-related applications is the combination of analog circuits with digital logic, while maintaining maximum performance at minimum power and cost. This combination presents a number of challenges beyond basic circuit design issues, ranging from technology choice and simulation techniques to noise and crosstalk. This paper focuses on recent CMOS design work addressing these issues, with specific attention to the area of high-speed serial data communication. Serial baseband data links, whether using fiber-optic or coaxial cables, incorporate coders and decoders, highspeed multiplexors and demultiplexors, and low-speed clock synchronization, along with phase-locked loops for high-speed clock synthesis and recovery (Figure 1). In addition, specialized analog circuits are typically required to interface with the particular medium (e.g., a laser driver and optical receiver circuit if a fiber-optic cable is used). The requirements and circuits for these specialized functions can vary widely depending on the transmission medium; however, the building blocks shown in Figure 1 are common to almost all serial data links and are the focus of this paper. The basic function, while conceptually simple, presents a number of significant design challenges due to the wide range of clock speeds and the mixture of analog and digital circuits required. For example, the Fibre Channel standard [l] specifies a maximum data rate of 1063 Mbaud, or a bit interval of 940 ps for the serial data. Clock generation and recovery and data retiming must operate at this high data rate, with a timing resolution of a fraction of the bit interval. Typically, these functions are implemented using custom analog circuits in order to achieve the stringent timing requirements and high speed; however, relatively few transistors are required (-500). At the parallel end of the data chain, frame processing (address resolution, sequence generation, etc.) is done at a multiple-byte level, at clock speeds of 50 MHz or even slower. The timing requirements are modest by current standards, but moderate transistor counts (-5 X lo’) are required to implement this function.

Gb/s fiber optic link adapter chip set

A pair of chips containing all of the required high-speed analog and digital circuitry for a fiber-optic date link with byte-wide interfaces, has been designed, fabricated, and tested at 1 Gb/s using a 1- mu m E/D (enhancement/depletion) MESFET technology. The transmitter chip takes a byte-wide parallel data stream and converts it to a serial signal suitable for driving a laser diode. The receiver chip takes an optical input and provides a retimed parallel data output synchronized with byte boundaries. It is concluded that such chips will find applications in computer data communication where packaging density and cost are important issues.<<ETX>>