Sergio Pernici

A CMOS low-distortion fully differential power amplifier with double nested Miller compensation

A four-stage fully differential power amplifier using a double-nested Miller compensated structure is presented. The multiple-loop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional three-stage amplifiers with nested Miller compensation. Design criteria and stability conditions for good stability of amplifiers using a multiple- (greater than two) loop topology are presented. The amplifier operates with a single power supply which has a minimum value of 3 V. With a 5-V supply, power dissipation is 10 mW and total harmonic distortion (THD) is -83 dB for a -V/sub p-p/ differential output signal at 10 kHz and a load of 50 Omega . With an 8 Omega load and for a 10-kHz, 4-V/sub p-p/ output signal, THD is -68 dB. The chip area is 0.625 mm/sup 2/ in a 1.5- mu m single-poly, double-metal, n-well CMOS technology. >

Low-voltage double-sampled /spl Sigma//spl Delta/ converters

In theory, double-sampling in second-order /spl Sigma//spl Delta/ analog-to-digital converters (ADC) can enhance the signal-to-noise ratio (SNR) by 15 dB. In practice however, the SNR performance is usually severely degraded because of mismatches occurring in switched-capacitors (SC). This paper introduces a simple method to solve this problem. Regarding /spl Sigma//spl Delta/ digital-to-analog converters (DAC), in addition to double-sampling, the accompanying use of internal decimation helps to relax the bandwidth requirements of the opamps. Both circuitries are to be operational to supply voltages as low as 1.5 V by using clock bootstrapping. Chip implementation is in double-poly, 2-metal technology featuring 0.5 /spl mu/m minimum channel lengths.

Low-voltage double-sampled ΣΔ converters

An obvious way of achieving higher signal-to-noise ratio in oversampled data converters is by increasing the effec- tive sampling rate. If all other components are kept constant, this translates into integrators with larger bandwidth that in turn results in higher overall power consumption. This work introduces the fully floating switched-capacitor configuration as a simple and robust technique to effectively double the sampling rate of oversampled data converters without compromising any aspect of the performance and yet maintaining the power levels of the conventional approach. The use of internal decimation in the switched-capacitor ladder structure of the digital-to-analog converter further helps in achieving the power budget goals. These converters have been implemented with circuitry capable of operating at a minimum supply voltage of 1.8 V under worst case process and temperature conditions and using clock bootstrapping for the transfer gates. The bootstrapping cir- cuit described here uses a single internal capacitor and has functionality that limits the maximum clock voltage to safe levels under a wide range of supply voltages. The prototype was fabricated in a 0.5- m CMOS double-poly technology. The analog-to-digital converter occupies a die area of 0.11 mm dissipating 550 W while the digital-to-analog converter occupies 0.28 mm dissipating 600 W.

A 2.7 V 11.8 mW baseband ADC with 72 dB dynamic range for GSM applications

A receive baseband analog-to-digital converter (ADC) for a GSM cellular radio system is presented. Low voltage and low power techniques have been applied across many aspects of the design. The circuit consists of two second-order double-sampled semi-bilinear /spl Sigma//spl Delta/ modulators followed by two 576-tap digital finite-impulse response (FIR) GSM-channel filters with offset calibration. The complete ADC achieves a dynamic range of 72 dB and dissipates 11.8 mW from a 2.7-V supply. The area is 1.6 mm/sup 2/ in a 0.5-/spl mu/m n-well double-poly triple-metal CMOS process.This paper describes a receive baseband ADC for a GSM cellular radio system. The circuit consists of two second-order double-sampled semi-bilinear /spl Sigma//spl Delta/ modulators followed by two 576-tap digital FIR GSM-channel filters with offset calibration. The complete A/D achieves a dynamic range of 72 dB and dissipates 11.8 mW from a 2.7 V supply. The area is 1.6 mm/sup 2/ in a 0.5 /spl mu/m N-well double-poly, triple-metal CMOS process.

A high-performance analog front-end 14-bit codec for 2.7-V digital cellular phones

A low-voltage, low-power, CMOS-programmable analog front-end IC for 2.7-V digital cellular phone applications is presented. The chip can be configured either as a classical A//spl mu/ law PCM codec or as a 14-bit uniform codec. The main objective of the uniform codec is to achieve a signal-to-noise (S/N) and a signal-to-total-harmonic-distortion (S/THD) ratio for the complete A/D and D/A paths better than 80 dB at full scale. A high-performance speech interface is made of a microphone preamplifier with about 0.5 mV offset and 1.3 /spl mu/V/sub rms/ input-referred noise for the transmit channel, and two power amplifiers capable of driving toads up to 27 /spl Omega/ or 50 nF with 4 V/sub pp/ output voltages and -80 dB of THD in the receive path. A tone generator that can also be used for ringing or DTMF signaling purposes, and a dedicated pulsewidth-modulated (PWM) output for a buzzer complete the chip functions. All programmable functions can be accessed via a standard four-wire control interface. This performance has been achieved from a 2.7-V supply with operative and standby power consumptions of 13 mW and 1.5 /spl mu/W, respectively. The chip area is 10.5 mm/sup 2/ (including scribe line) in a 0.5-/spl mu/m n-well CMOS technology.

A 5-V CMOS programmable acoustic front-end for ISDN terminals and digital telephone sets

A 5-V CMOS programmable acoustic front-end IC for ISDN terminal and digital telephone set applications is presented. The chip performs PCM codec and filter functions, fulfilling all D3/D4 and CCITT specs. Moreover, it implements the main analog interfaces required for the speech channel (low-noise microphone preamplifier, earpiece and loudspeaker drivers, sidetone, antilarsen control) and tone/ring/DTMF generation without external components. The device can be controlled by a microprocessor or a HDLC controller via a four wire separated control interface or by means of a serial control channel multiplexed with the PCM voice/data channel in a GCI compatible format. Chip area is 30 mm/sup 2/ in a 1.5-/spl mu/m CMOS technology. The active/stand-by power consumption is 60 mW/0.2 mW from a single 5-V supply. All circuits are designed to meet performance objectives over a voltage range from 4.5 V to 5.5 V and a temperature range from -40/spl deg/C up to 85/spl deg/C. >

Fully integrated voiceband codec in a standard digital CMOS technology

A 2.7-V complete voiceband codec with high-performance speech interfaces is presented. It includes a low-noise microphone preamplifier and loudspeaker/earpiece drivers. In the 4-kHz signal bandwidth, the ADC achieves a dynamic range of 80 dB and a full scale S/(THD + N) ratio of 71 dB, while the DAC performs 84 dB and 75 dB, respectively. These performances have been obtained in a pure digital low-cost CMOS process. The only components used are standard nMOS and pMOS transistors, parasitic vertical PNP bipolar transistors, unsalicided poly resistors, nonlinear poly-nwell capacitors, and a few small linear capacitors made with a sandwich of five metals and poly. The active area is 2.7 mm/sup 2/ in a 0.35-/spl mu/m, five metal levels, standard digital CMOS technology. Power dissipation is 12 mW. The cell can be easily migrated in more advanced processes with area reduction. A migration in a 0.18-/spl mu/m digital CMOS process has been achieved.

A 5V CMOS Programmable Acoustic Front-End for ISDN Terminals and Digital Telephone Sets

A 5V programmable acoustic front-end IC for ISDN terminal and digital telephone set applications is presented. The chip performs PCM codec and filter functions fulfilling and exceeding all D3/D4 and CCITT specs. It implements the analog interfaces required for the speech (low noise microphone preamplifier, earpiece and loudspeaker drivers, sidetone, antilarsen control) and tone/ring/DTMF generation without external components. The device can be controlled by a microprocessor or a HDLC controller via a separate four wire control interface or by means of a serial control channel multiplexed with the PCM voice/data in a GCI compatible format. Chip area is 30 mm2 in a 1.5¿ CMOS technology. Active/stand-by power consumption is 60mW/0.2mW from a single 5V supply.

A high-performance analog front-end 13-bits linear codec for 3V digital cellular phones

A low-voltage, low-power, CMOS programmable Analog Front-End IC for 3 V digital cellular phone applications is presented. The chip can be configured either as a classical A//spl mu/ law PCM codec or as a 13-bits linear codec. Its high performance speech interface results in a microphone preamplifier with about 0.5 mV offset and 1.3 /spl mu/V/sub rms/ input-referred noise for the transmit channel, while it is capable of driving loads up to 27 /spl Omega/ or 50 nF with 4 V/sub pp/, output voltages and -80 dB of THD in the receive path. A tone generator that can also be used for ringing or DTMF signaling purpose, and a dedicated pulse-width modulated output for a buzzer complete the chip functions. All programmable functions can be accessed via a standard four wire control interface. These performances have been achieved from a 3 V supply with operative and stand-by power consumptions of 21 mW and 1.5 /spl mu/W, respectively. Chip area is 22.7 mm/sup 2/ in a 0.8 /spl mu/ CMOS process.

A CMOS fully integrated antilarsen system for digital telephones

An integrated CMOS antilarson system that requires no external components is presented. Speech time constants as long as 100 ms are digitally realized. A 12-dB antilarsen depth and a 6-dB hysteresis are provided for the specific application where the system is involved, but both of them and the voice time constants can be register programmed to different values. The extra area added to the chip for the antilarsen function is only 0.5 mm/sup 2/ in a 1.5- mu m CMOS technology. >