Alberto Poveda

Application of sliding-mode control to the design of a buck-based sinusoidal generator

This paper is devoted to the design of a sliding-mode control scheme for a buck-based inverter, with programmable amplitude, frequency, and DC offset, with no external sinusoidal reference required. A general procedure for obtaining an autonomous (time independent) switching surface from a time-dependent one is presented. For this surface, the system exhibits a zeroth-order dynamics in sliding motion. On the other hand, from the sliding-domain analysis, a set of design restrictions is established in terms of the inverter output filter Bode diagram and the output signal parameters (amplitude, frequency and DC offset), facilitating the subsequent design procedure. The control scheme is robust with respect to both power-stage parameter variations and external disturbances and can be implemented by means of conventional electronic circuitry. Simulations and experimental results for both reactive and nonlinear loads are presented.

Analysis of a bidirectional coupled-inductor Cuk converter operating in sliding mode

Analytic models for a bidirectional coupled-inductor Cuk converter operating in sliding mode are described. Using a linear combination of the converter four state variable errors as a general switching surface, the expression for the equivalent control is derived and the coordinates of the equilibrium point are obtained. Particular cases of the general switching surface are subsequently analyzed in detail: (1) surfaces for ideal line regulation, (2) surfaces for ideal load regulation, and (3) surfaces for hysteretic current control. Simulation results verifying the analytical predictions are presented.

Large-signal modeling and simulation of switching DC-DC converters

A general nonlinear continuous formulation procedure for large-signal analysis of switching DC-DC converters is presented. The method can be applied in either of the two conduction modes, and it is easily programmed for computer-aided analysis with small simulation time. A boost regulator operating in constant-frequency current-programmed mode is used to illustrate the application of the method. A stability graph is subsequently developed to facilitate the design of DC-DC switching regulators for large-signal applications. The graph provides an estimation of the values of input voltage and load resistance leading to a stable regulator behavior.

Bandwidth limits in PWM switching amplifiers

PWM buck switching power converters are good candidates for high efficiency power amplification of arbitrary band-limited signals. The correlation between the signal bandwidth and the switching frequency, in turn related to switching losses, imposes practical limits for high bandwidth applications. Stringent specifications appear in such applications as audio amplifiers (kHz signal bandwidths), and lately, in fast envelope tracking power amplifiers (MHz signal bandwidths) for the Envelope Elimination and Restoration technique in polar RF power amplification. Bandwidth limitations in PWM amplifiers are explored in this work by proposing design criteria for obtaining the switching frequency to signal bandwidth ratio (fs/fx) so as to guarantee a given aliasing error. To achieve that purpose, PWM spectra are reviewed for single tone, two-tone and multitone signals. Subsequently, by taking into account the analogy between PWM and FM spectra, bandwidths around the switching frequency are estimated by extending Carsons rule to an arbitrary error. This allows obtaining an extension of the Nyquist criterion for pulse-width modulation. System-level simulation results are reported to validate the analysis, showing that the conventional fs/fx factor used in the power converter design field might be too conservative

Energy optimization of tapered buffers for CMOS on-chip switching power converters

This work presents a model to determine the power consumption of tapered buffers, validating its results with transistor-level simulations. Focusing on their application as gate drivers for high-frequency on-chip switching power converters, the need for a fall-rise time evaluation at the output of the tapered buffer is discussed. Consequently, the output fall-rise time is modeled and validated by means of simulations. Given the linear relation between the fall-rise time and the switching losses of the power MOSFET, an optimized design procedure is proposed to concurrently minimize the switching losses of the tapered buffer together with the power MOSFET switching losses. The work concludes with a design example for a 15000 /spl mu/m-width PMOS transistor, presenting an optimum tapering factor of 21, for a specific 0.35 /spl mu/m standard CMOS technology.

Efficiency-oriented switching frequency tuning for a buck switching power converter

Successful on-chip integration of a buck switching power converter concurrently requires the fulfillment of stringent specifications, namely low silicon area occupancy, low relative output ripple, proper transient response, whilst assuring high efficiency. The paper focuses on efficiency optimization of a buck converter suited to CMOS integration. Switching and conduction energy loss models are discussed, both for continuous and discontinuous conduction modes. Minimization of overall power losses yields an optimum law that continuously tunes the switching frequency as a function of load current. A practical piecewise linear approximation is proposed and applied to transient simulations and to compute overall efficiency. The work concludes by comparing the efficiency-oriented optimum frequency tuning law to that intrinsically obtained from output voltage hysteretic control. Numerical examples consider a standard CMOS 0.35 /spl mu/m technology.

Optimized design of MOS capacitors in standard CMOS technology and evaluation of their Equivalent Series Resistance for power applications

An analytical study of the MOSFET-based capacitor is presented. This highly dense capacitive structure, suited to integrated circuits, is studied specifically for power applications by providing design guidelines for achieving minimum equivalent series resistance (ESR). The work includes layout strategies in standard digital CMOS technologies to provide optimal ESR, a design procedure for a target impedance at a given frequency, as well as a performance comparison with other on-chip capacitive structures such as poly-poly and metal-metal capacitors. The results are applicable for on-chip power circuits such as output filter stages in future integrated switching power converters, switched capacitor power converters, or decoupling circuits in high-performance on-chip power distributing networks.

Compensating networks for sliding-mode control

The introduction of compensating networks in sliding-mode controlled dc-to-dc switching converters improves the converter start-up behaviour and reduces steady-state errors in the circuit output response. The ideal equivalence among sliding regimes and PWM control responses in nonlinear dynamical systems is used to model the converter dynamics around the equilibrium point. A sliding-mode controlled boost regulator illustrates the application of the method.

Computer-aided discrete-time large-signal analysis of switching regulators

A computer program based on a general nonlinear discrete formulation procedure for large-signal analysis of switching regulators is introduced. The program provides both time-domain and state-trajectory simulation of converter state variables under different control strategies in either of two conduction modes. As a result, the regulator asymptotic stability can be predicted for large-signal operation. Experimental results verify the theoretical predictions. >

Minimum time control of a buck converter by means of fuzzy logic approximation

This paper investigates the use of fuzzy logic to implement some nonlinear control laws in bidirectional power converters. The authors design a minimum time control scheme of a buck power converter by means of fuzzy logic approximation. The proposed controller is implemented by means of an analog hardware architecture which is able to efficiently implement neuro-fuzzy models. By combining the main features of digital and analog alternatives, it is possible to provide a high degree of flexibility (in terms of number of inputs, number of membership functions per input and number of fuzzy rules) when handling real world tasks. Also, the authors have created a program for validating, via software, the proposed architecture. Computer simulation results for a buck power converter structure illustrate the design and the implementation. VLSI ASIC mixed-mode implementation details are also included.